IEICE TRANSACTIONS on Electronics
Trends of On-Chip Interconnects in Deep Sub-Micron VLSI
Summary :
This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.392-394
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.392
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
- Interconnect Technique
Authors
Keyword
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Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, Takayasu SAKURAI, "Trends of On-Chip Interconnects in Deep Sub-Micron VLSI" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 392-394, March 2006, doi: 10.1093/ietele/e89-c.3.392.
Abstract: This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.392/_p
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@ARTICLE{e89-c_3_392,
author={Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Trends of On-Chip Interconnects in Deep Sub-Micron VLSI},
year={2006},
volume={E89-C},
number={3},
pages={392-394},
abstract={This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.},
keywords={},
doi={10.1093/ietele/e89-c.3.392},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Trends of On-Chip Interconnects in Deep Sub-Micron VLSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 392
EP - 394
AU - Danardono Dwi ANTONO
AU - Kenichi INAGAKI
AU - Hiroshi KAWAGUCHI
AU - Takayasu SAKURAI
PY - 2006
DO - 10.1093/ietele/e89-c.3.392
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.
ER -
English
