IEICE TRANSACTIONS on Electronics
Power Optimization of an 8051-Compliant IP Microcontroller
Summary :
Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.597-600
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.597
- Type of Manuscript
- Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
- Category
Authors
Keyword
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Luca FANUCCI, Sergio SAPONARA, Alexander MORELLO, "Power Optimization of an 8051-Compliant IP Microcontroller" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 597-600, April 2005, doi: 10.1093/ietele/e88-c.4.597.
Abstract: Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.597/_p
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@ARTICLE{e88-c_4_597,
author={Luca FANUCCI, Sergio SAPONARA, Alexander MORELLO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Optimization of an 8051-Compliant IP Microcontroller},
year={2005},
volume={E88-C},
number={4},
pages={597-600},
abstract={Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.},
keywords={},
doi={10.1093/ietele/e88-c.4.597},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Power Optimization of an 8051-Compliant IP Microcontroller
T2 - IEICE TRANSACTIONS on Electronics
SP - 597
EP - 600
AU - Luca FANUCCI
AU - Sergio SAPONARA
AU - Alexander MORELLO
PY - 2005
DO - 10.1093/ietele/e88-c.4.597
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.
ER -
English
