IEICE TRANSACTIONS on Electronics
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones
Summary :
We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through µI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 µA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.528-535
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.528
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
Authors
Makoto ISHIKAWA
Tatsuya KAMEI
Yuki KONDO
Masanao YAMAOKA
Yasuhisa SHIMAZAKI
Motokazu OZAWA
Saneaki TAMAKI
Mikio FURUYAMA
Tadashi HOSHI
Fumio ARAKAWA
Osamu NISHII
Kenji HIROSE
Shinichi YOSHIOKA
Toshihiro HATTORI
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Makoto ISHIKAWA, Tatsuya KAMEI, Yuki KONDO, Masanao YAMAOKA, Yasuhisa SHIMAZAKI, Motokazu OZAWA, Saneaki TAMAKI, Mikio FURUYAMA, Tadashi HOSHI, Fumio ARAKAWA, Osamu NISHII, Kenji HIROSE, Shinichi YOSHIOKA, Toshihiro HATTORI, "A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 528-535, April 2005, doi: 10.1093/ietele/e88-c.4.528.
Abstract: We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through µI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 µA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.528/_p
Copy
@ARTICLE{e88-c_4_528,
author={Makoto ISHIKAWA, Tatsuya KAMEI, Yuki KONDO, Masanao YAMAOKA, Yasuhisa SHIMAZAKI, Motokazu OZAWA, Saneaki TAMAKI, Mikio FURUYAMA, Tadashi HOSHI, Fumio ARAKAWA, Osamu NISHII, Kenji HIROSE, Shinichi YOSHIOKA, Toshihiro HATTORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones},
year={2005},
volume={E88-C},
number={4},
pages={528-535},
abstract={We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through µI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 µA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.},
keywords={},
doi={10.1093/ietele/e88-c.4.528},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones
T2 - IEICE TRANSACTIONS on Electronics
SP - 528
EP - 535
AU - Makoto ISHIKAWA
AU - Tatsuya KAMEI
AU - Yuki KONDO
AU - Masanao YAMAOKA
AU - Yasuhisa SHIMAZAKI
AU - Motokazu OZAWA
AU - Saneaki TAMAKI
AU - Mikio FURUYAMA
AU - Tadashi HOSHI
AU - Fumio ARAKAWA
AU - Osamu NISHII
AU - Kenji HIROSE
AU - Shinichi YOSHIOKA
AU - Toshihiro HATTORI
PY - 2005
DO - 10.1093/ietele/e88-c.4.528
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through µI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 µA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.
ER -
English
