IEICE TRANSACTIONS on Electronics
A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
Summary :
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.590-596
- Publication Date
- 1997/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Integrated Electronics
Authors
Masataka MINAMI
Nagatoshi OHKI
Hiroshi ISHIDA
Toshiaki YAMANAKA
Akihiro SHIMIZU
Koichiro ISHIBASHI
Akira SATOH
Tokuo KURE
Takashi NISHIDA
Takahiro NAGANO
Keyword
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Masataka MINAMI, Nagatoshi OHKI, Hiroshi ISHIDA, Toshiaki YAMANAKA, Akihiro SHIMIZU, Koichiro ISHIBASHI, Akira SATOH, Tokuo KURE, Takashi NISHIDA, Takahiro NAGANO, "A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 4, pp. 590-596, April 1997, doi: .
Abstract: A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_4_590/_p
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@ARTICLE{e80-c_4_590,
author={Masataka MINAMI, Nagatoshi OHKI, Hiroshi ISHIDA, Toshiaki YAMANAKA, Akihiro SHIMIZU, Koichiro ISHIBASHI, Akira SATOH, Tokuo KURE, Takashi NISHIDA, Takahiro NAGANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory},
year={1997},
volume={E80-C},
number={4},
pages={590-596},
abstract={A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 590
EP - 596
AU - Masataka MINAMI
AU - Nagatoshi OHKI
AU - Hiroshi ISHIDA
AU - Toshiaki YAMANAKA
AU - Akihiro SHIMIZU
AU - Koichiro ISHIBASHI
AU - Akira SATOH
AU - Tokuo KURE
AU - Takashi NISHIDA
AU - Takahiro NAGANO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.
ER -
English
