A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.