In this work, a divide-by-2 injection locked frequency divider (ILFD) operating in the V-band with a low DC power consumption has been developed in a commercial 0.13-µm Si RFCMOS technology. The bias current path was separated from the injection signal path, which enabled a small supply voltage of 0.5 V, leading to a DC power consumption of only 0.31 mW. To the authors' best knowledge, this is the lowest power consumption reported for mm-wave ILFDs at the point of writing. All inductors and interconnection lines were designed based on EM (electromagnetic) simulator for precise prediction of circuit performance. With varactor tuning voltage ranged for 0-1.2 V, the free-running oscillation frequency varied from 27.43 to 28.06 GHz. At 0 dBm input power, the frequency divider exhibited a locking range of 5.8 GHz from 53 to 58.8 GHz without external tuning mechanism. The fabricated circuit size is 0.72 mm 0.62 mm including the RF and DC supply pads.

This paper presents a G-band triple-push voltage controlled oscillator (VCO) operating around 177GHz. The VCO, implemented in a commercial 0.13-µm RFCMOS technology, adopts a triple-push topology that is composed of 3 symmetrically coupled identical Colpitts sub-oscillators. Oscillation frequency can be tuned from 175.9GHz to 178.4GHz with varactor tuning voltage swept from 0 to 1.2V. The calibrated output power ranged from -19.7dBm to -16.6dBm depending on the oscillation frequency. The measured phase noise of the VCO is -80.2dBc/Hz at 1MHz offset. The results clearly demonstrate the possibility of applying triple-push topology for VCOs operating beyond 100GHz, enabling various high frequency applications that require tunable frequency sources.

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13 µm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT. The measured gain was 18.6 dB with VDD = 1.2 V and increased up to 20.2 dB with VDD = 1.8 V at 66 GHz. The measured NF showed a minimum value of 7.0 dB at 62 GHz. DC power consumption was 24 mW with VDD = 1.2 V. The size of the fabricated circuit is as compact as 0.45 mm 0.69 mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6 dB and average NF degradation of 1.3 dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills.

In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (Cegs, Cegd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (fT) and maximum oscillation frequency (fmax) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers Nf on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, fT is slightly degraded but fmax is significantly improved, especially for larger Nf, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.