IEICE TRANSACTIONS on Fundamentals
SAR ADC Algorithm with Redundancy and Digital Error Correction
Summary :
This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.2 pp.415-423
- Publication Date
- 2010/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.415
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Tomohiko OGAWA
Haruo KOBAYASHI
Yosuke TAKAHASHI
Nobukazu TAKAI
Masao HOTTA
Hao SAN
Tatsuji MATSUURA
Akira ABE
Katsuyoshi YAGI
Toshihiko MORI
Keyword
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Tomohiko OGAWA, Haruo KOBAYASHI, Yosuke TAKAHASHI, Nobukazu TAKAI, Masao HOTTA, Hao SAN, Tatsuji MATSUURA, Akira ABE, Katsuyoshi YAGI, Toshihiko MORI, "SAR ADC Algorithm with Redundancy and Digital Error Correction" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 415-423, February 2010, doi: 10.1587/transfun.E93.A.415.
Abstract: This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.415/_p
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@ARTICLE{e93-a_2_415,
author={Tomohiko OGAWA, Haruo KOBAYASHI, Yosuke TAKAHASHI, Nobukazu TAKAI, Masao HOTTA, Hao SAN, Tatsuji MATSUURA, Akira ABE, Katsuyoshi YAGI, Toshihiko MORI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SAR ADC Algorithm with Redundancy and Digital Error Correction},
year={2010},
volume={E93-A},
number={2},
pages={415-423},
abstract={This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.},
keywords={},
doi={10.1587/transfun.E93.A.415},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - SAR ADC Algorithm with Redundancy and Digital Error Correction
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 415
EP - 423
AU - Tomohiko OGAWA
AU - Haruo KOBAYASHI
AU - Yosuke TAKAHASHI
AU - Nobukazu TAKAI
AU - Masao HOTTA
AU - Hao SAN
AU - Tatsuji MATSUURA
AU - Akira ABE
AU - Katsuyoshi YAGI
AU - Toshihiko MORI
PY - 2010
DO - 10.1587/transfun.E93.A.415
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.
ER -
English
