IEICE TRANSACTIONS on Electronics
A Low-Cost Stimulus Design for Linearity Test in SAR ADCs
Summary :
The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.6 pp.538-545
- Publication Date
- 2014/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.538
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
An-Sheng CHAO
National Cheng Kung University
Cheng-Wu LIN
National Cheng Kung University
Hsin-Wen TING
National Kaohsiung University of Applied Sciences
Soon-Jyh CHANG
National Cheng Kung University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
An-Sheng CHAO, Cheng-Wu LIN, Hsin-Wen TING, Soon-Jyh CHANG, "A Low-Cost Stimulus Design for Linearity Test in SAR ADCs" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 6, pp. 538-545, June 2014, doi: 10.1587/transele.E97.C.538.
Abstract: The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.538/_p
Copy
@ARTICLE{e97-c_6_538,
author={An-Sheng CHAO, Cheng-Wu LIN, Hsin-Wen TING, Soon-Jyh CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Cost Stimulus Design for Linearity Test in SAR ADCs},
year={2014},
volume={E97-C},
number={6},
pages={538-545},
abstract={The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.},
keywords={},
doi={10.1587/transele.E97.C.538},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Low-Cost Stimulus Design for Linearity Test in SAR ADCs
T2 - IEICE TRANSACTIONS on Electronics
SP - 538
EP - 545
AU - An-Sheng CHAO
AU - Cheng-Wu LIN
AU - Hsin-Wen TING
AU - Soon-Jyh CHANG
PY - 2014
DO - 10.1587/transele.E97.C.538
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2014
AB - The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.
ER -
English
