IEICE TRANSACTIONS on Information
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Summary :
This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.9 pp.1986-1993
- Publication Date
- 2013/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.1986
- Type of Manuscript
- Special Section PAPER (Special Section on Dependable Computing)
- Category
Authors
Hiroyuki YOTSUYANAGI
Univ. of Tokushima
Hiroyuki MAKIMOTO
Univ. of Tokushima
Takanobu NIMIYA
Univ. of Tokushima
Masaki HASHIZUME
Univ. of Tokushima
Keyword
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Hiroyuki YOTSUYANAGI, Hiroyuki MAKIMOTO, Takanobu NIMIYA, Masaki HASHIZUME, "On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 9, pp. 1986-1993, September 2013, doi: 10.1587/transinf.E96.D.1986.
Abstract: This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1986/_p
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@ARTICLE{e96-d_9_1986,
author={Hiroyuki YOTSUYANAGI, Hiroyuki MAKIMOTO, Takanobu NIMIYA, Masaki HASHIZUME, },
journal={IEICE TRANSACTIONS on Information},
title={On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan},
year={2013},
volume={E96-D},
number={9},
pages={1986-1993},
abstract={This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.},
keywords={},
doi={10.1587/transinf.E96.D.1986},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
T2 - IEICE TRANSACTIONS on Information
SP - 1986
EP - 1993
AU - Hiroyuki YOTSUYANAGI
AU - Hiroyuki MAKIMOTO
AU - Takanobu NIMIYA
AU - Masaki HASHIZUME
PY - 2013
DO - 10.1587/transinf.E96.D.1986
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2013
AB - This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.
ER -
English
