IEICE TRANSACTIONS on Information
Proposal of Testable Multi-Context FPGA Architecture
Summary :
Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.
- Publication
- IEICE TRANSACTIONS on Information Vol.E89-D No.5 pp.1687-1693
- Publication Date
- 2006/05/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e89-d.5.1687
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kazuteru NAMBA, Hideo ITO, "Proposal of Testable Multi-Context FPGA Architecture" in IEICE TRANSACTIONS on Information,
vol. E89-D, no. 5, pp. 1687-1693, May 2006, doi: 10.1093/ietisy/e89-d.5.1687.
Abstract: Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.5.1687/_p
Copy
@ARTICLE{e89-d_5_1687,
author={Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Proposal of Testable Multi-Context FPGA Architecture},
year={2006},
volume={E89-D},
number={5},
pages={1687-1693},
abstract={Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.},
keywords={},
doi={10.1093/ietisy/e89-d.5.1687},
ISSN={1745-1361},
month={May},}
Copy
TY - JOUR
TI - Proposal of Testable Multi-Context FPGA Architecture
T2 - IEICE TRANSACTIONS on Information
SP - 1687
EP - 1693
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2006
DO - 10.1093/ietisy/e89-d.5.1687
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2006
AB - Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.
ER -
English
