IEICE TRANSACTIONS on Information
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
Summary :
A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.10 pp.2783-2791
- Publication Date
- 2010/10/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.2783
- Type of Manuscript
- PAPER
- Category
- Information Network
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Nobutaka KITO, Kensuke HANAI, Naofumi TAKAGI, "A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 10, pp. 2783-2791, October 2010, doi: 10.1587/transinf.E93.D.2783.
Abstract: A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2783/_p
Copy
@ARTICLE{e93-d_10_2783,
author={Nobutaka KITO, Kensuke HANAI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Information},
title={A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier},
year={2010},
volume={E93-D},
number={10},
pages={2783-2791},
abstract={A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.},
keywords={},
doi={10.1587/transinf.E93.D.2783},
ISSN={1745-1361},
month={October},}
Copy
TY - JOUR
TI - A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
T2 - IEICE TRANSACTIONS on Information
SP - 2783
EP - 2791
AU - Nobutaka KITO
AU - Kensuke HANAI
AU - Naofumi TAKAGI
PY - 2010
DO - 10.1587/transinf.E93.D.2783
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2010
AB - A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.
ER -
English
