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IEICE TRANSACTIONS on Information

Design and Optimization of Transparency-Based TAM for SoC Test

Tomokazu YONEDA, Akiko SHUTO, Hideyuki ICHIHARA, Tomoo INOUE, Hideo FUJIWARA

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Summary :

We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

Publication
IEICE TRANSACTIONS on Information Vol.E93-D No.6 pp.1549-1559
Publication Date
2010/06/01
Publicized
Online ISSN
1745-1361
DOI
10.1587/transinf.E93.D.1549
Type of Manuscript
PAPER
Category
Information Network

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