We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.
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Tomokazu YONEDA, Akiko SHUTO, Hideyuki ICHIHARA, Tomoo INOUE, Hideo FUJIWARA, "Design and Optimization of Transparency-Based TAM for SoC Test" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 6, pp. 1549-1559, June 2010, doi: 10.1587/transinf.E93.D.1549.
Abstract: We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1549/_p
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@ARTICLE{e93-d_6_1549,
author={Tomokazu YONEDA, Akiko SHUTO, Hideyuki ICHIHARA, Tomoo INOUE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Optimization of Transparency-Based TAM for SoC Test},
year={2010},
volume={E93-D},
number={6},
pages={1549-1559},
abstract={We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.},
keywords={},
doi={10.1587/transinf.E93.D.1549},
ISSN={1745-1361},
month={June},}
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TY - JOUR
TI - Design and Optimization of Transparency-Based TAM for SoC Test
T2 - IEICE TRANSACTIONS on Information
SP - 1549
EP - 1559
AU - Tomokazu YONEDA
AU - Akiko SHUTO
AU - Hideyuki ICHIHARA
AU - Tomoo INOUE
AU - Hideo FUJIWARA
PY - 2010
DO - 10.1587/transinf.E93.D.1549
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2010
AB - We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.
ER -