IEICE TRANSACTIONS on Electronics
Electrical Transport in Nano-Scale Silicon Devices
Summary :
This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.
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- IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1037-1042
- Publication Date
- 2001/08/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Silicon Nanodevices)
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Hisao KAWAURA, Toshitsugu SAKAMOTO, "Electrical Transport in Nano-Scale Silicon Devices" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1037-1042, August 2001, doi: .
Abstract: This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1037/_p
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@ARTICLE{e84-c_8_1037,
author={Hisao KAWAURA, Toshitsugu SAKAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Electrical Transport in Nano-Scale Silicon Devices},
year={2001},
volume={E84-C},
number={8},
pages={1037-1042},
abstract={This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Electrical Transport in Nano-Scale Silicon Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 1037
EP - 1042
AU - Hisao KAWAURA
AU - Toshitsugu SAKAMOTO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.
ER -
English
