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[Author] Toshitsugu SAKAMOTO(5hit)

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  • 28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation

    Xu BAI  Ryusuke NEBASHI  Makoto MIYAMURA  Kazunori FUNAHASHI  Naoki BANNO  Koichiro OKAMOTO  Hideaki NUMATA  Noriyuki IGUCHI  Tadahiko SUGIBAYASHI  Toshitsugu SAKAMOTO  Munehiro TADA  

     
    BRIEF PAPER

      Pubricized:
    2022/06/27
      Vol:
    E105-C No:10
      Page(s):
    627-630

    A static timing analysis (STA) tool for a 28nm atom-switch FPGA (AS-FPGA) is introduced to validate the signal delay of an application circuit before implementation. High accuracy of the STA tool is confirmed by implementing a practical application circuit on the 28nm AS-FPGA. Moreover, dramatic improvement of delay and power is demonstrated in comparison with a previous 40nm AS-FPGA.

  • A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA

    Ryutaro DOI  Xu BAI  Toshitsugu SAKAMOTO  Masanori HASHIMOTO  

     
    PAPER

      Vol:
    E103-A No:12
      Page(s):
    1447-1455

    FPGA that exploits via-switches, which are a kind of non-volatile resistive RAMs, for crossbar implementation is attracting attention due to its high integration density and energy efficiency. Via-switch crossbar is responsible for the signal routing in the interconnections by changing on/off-states of via-switches. To verify the via-switch crossbar functionality after manufacturing, fault testing that checks whether we can turn on/off via-switches normally is essential. This paper confirms that a general differential pair comparator successfully discriminates on/off-states of via-switches, and clarifies fault modes of a via-switch by transistor-level SPICE simulation that injects stuck-on/off faults to atom switch and varistor, where a via-switch consists of two atom switches and two varistors. We then propose a fault diagnosis methodology for via-switches in the crossbar that diagnoses the fault modes according to the comparator response difference between the normal and faulty via-switches. The proposed method achieves 100% fault detection by checking the comparator responses after turning on/off the via-switch. In case that the number of faulty components in a via-switch is one, the ratio of the fault diagnosis, which exactly identifies the faulty varistor and atom switch inside the faulty via-switch, is 100%, and in case of up to two faults, the fault diagnosis ratio is 79%.

  • Solid-Electrolyte Nanometer Switch

    Naoki BANNO  Toshitsugu SAKAMOTO  Noriyuki IGUCHI  Hisao KAWAURA  Shunichi KAERIYAMA  Masayuki MIZUNO  Kozuya TERABE  Tsuyoshi HASEGAWA  Masakazu AONO  

     
    INVITED PAPER

      Vol:
    E89-C No:11
      Page(s):
    1492-1498

    We have developed a solid-electrolyte nonvolatile switch (here we refer as NanoBridge) with a low ON resistance and its small size. When we use a NanoBridge to switch elements in a programmable logic device, the chip size (or die cost) can be reduced and performance (speed and power consumption) can be enhanced. Developing this application required solving a couple of problems. First, the switching voltage of the NanoBridge (0.3 V) needed to be larger than the operating voltage of the logic circuit (>1 V). Second, the programming current (>1 mA) needed to be suppressed to avoid large power consumption. We demonstrate how the Nanobridge enhances the switching voltage and reduces the programming current.

  • Electrical Transport in Nano-Scale Silicon Devices

    Hisao KAWAURA  Toshitsugu SAKAMOTO  

     
    INVITED PAPER

      Vol:
    E84-C No:8
      Page(s):
    1037-1042

    This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.

  • Individual Carrier Traps in GaAs/AlxGa1-xAs Heterostructures

    Toshitsugu SAKAMOTO  Yasunobu NAKAMURA  Kazuo NAKAMURA  

     
    PAPER

      Vol:
    E79-C No:11
      Page(s):
    1590-1595

    We study individual carrier traps in a GaAs/AlxGa1-xAs heterostructure by observing random telegraph signals. A narrow channel, which is formed in a split gate device, is shifted by independently controlling the voltage applied to each part of the split gate. RTSs can be observed only when the traps are close to the channel and the energy levels of the traps are within a few kBT of the Fermi level. This type of measurement reveals the locations and the energy distributions of the traps. We also discuss the situation in which two trap levels are at the Fermi level simultaneously. In this condition the two RTSs do not occur at the same time, but they do interact with each other. This implies that there is an electrostatic interaction between the two trappings.