Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n^- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

Single-drain PMOSFET's with a very shallow source and drain were fabricated using a new doping method called rapid vapor-phase doping (RVD). This process is carried out in hydrogen atmosphere using B₂H₆ as a source gas. By varying flow rate of B₂H₆ and the doping time, shallow boron doped layers which are suitable for source and drain regions of MOSFET's are formed. The fabricated RVD-PMOSFET's have 50-nm source and drain regions with peak concentration of 410²⁰ cm^-3 which were formed under the condition of 800, B₂H₆ flow rate of 50 ml/min. The junction depth was one third of those formed by conventional low-energy BF₂ ion implantation. RVD-PMOSFET's showed normal operation down to poly-Si gate length L_g of 0.18 µm. The advantage of shallow junction was clearly shown by the threshold voltage roll-off characteristics, that is, it was suppressed down to 0.18 µm, whereas in conventional device, roll-off occurred below 0.6 µm. This better short channel behavior suggests that RVD forms shallow source and drain regions with weaker lateral diffusion. This result confirms that RVD is an effective method for forming shallow junctions for MOSFET's.

A new evaluation technique of hot carrier degradation is proposed and applied to practical evaluation of p-channel polycrystalline silicon thin film transistors (TFT). The proposed technique introduces emission microscopy which is particularly effective for evaluating TFT devices. We have developed an automatic measurement system in which measurement of the electrical characteristics and monitoring the photo emission are done simultaneously. Using this system, we have identified the dominant mechanism of hot carrier degradation in TFTs, and evaluated the effect of plasma hydrogenation on hot carrier degradation.

Optical and electrical measurements of thin film n-channel SOI-MOSFETs reveal that the exponential tail in photon emission spectra originates from electron-hole recombination. Bremsstrahlung radiation model as a physical mechanism of photon emission was experimentally negated. Negative threshold voltage shift at the initial stage of high field stress is found to be caused by hole trapping in buried oxide. Subsequent turnover characteristics is explained by a competing process between electron trapping in the front gate oxide and hole trapping in the buried oxide. As to the degradation of transconductance, generated surface state as well as trapped holes in the buried oxide which reduce vertical electric field in SOI film are involved in the complicate degradation of transconductance.

This paper describes the formation of ultra-thin tantalum oxide capacitors, using rapid thermal nitridation (RTN) of the storage-node polycrystalline-silicon surface prior to low-pressure chemical vapor deposition of tantalum oxide, using penta-ethoxy-tantalum [(Ta(OC₂H₅)₅) and oxygen gas mixture. The films are annealed at 600-900 in dry O₂ atmosphere. Densification of the as-deposited film by annealing in dry O₂ is indispensable to the formation of highly reliable ultra-thin tantalum oxide capacitors. The RTN treatment reduces the SiO₂ equivalent thickness and leakage current of the tantalum oxide film, and improves the time dependent dielectric breakdown characteristics of the film.

Thin (Ba_0.75Sr_0.25)TiO₃ (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (t_eq) of 0.47 nm, and a leak current density about 110^-8 A/cm² were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba_1-xSR_xTiO₃) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

A new method for the DRAM soft-error evaluation was developed. By using a focused proton microprobe as a radiation source, and scanning it on a memory cell plane, local sensitive structure of memory cells against soft-errors could be investigated with a form of the susceptibility mapping. Cell mode and bit-line mode soft-errors could be clearly distinguished by controlling the incident location and the proton dose, and it was also found that the incident beam within 4 µm around the monitored memory cell caused the soft-error. The retrograde well formed by the MeV ion implantation technology was examined by this method. It was confirmed that the B⁺ layers in the retrograde well were a sufficient barrier against the charge collection. The generation rate of the electron-hole pairs and the charge collection into n⁺ layers with a retrograde well and a conventional well were estimated by the device simulator, and were explained the experimental results.

A design rule relaxation approach is one of the most important requirements for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high density DRAMs with the minimum development of a scaled-down MOS structure and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-line cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 times wider isolation width. The Boosted Dual Word-Line scheme provides 2ⁿ times wider 1st Al pitch on memory cell array, double word-line driver pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line scheme provides several times depth of focus (DOF) for 1st Al wiring which gives several times higher storage node and larger capacitance for capacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.91.8 µm² memory cell.

New critical-dimension controlling technique of off-axis illumination for aperiodic patterns has been developed. By means of arranging not-imaging additional pattern near 0.25 micron isolated patterns, the depth of focus of an isolated pattern was improved as well as the periodic patterns. Simulation and experimental results were verified on a 0.48 numerical-aperture, KrF excimer laser stepper. Using new deep-ultra-violet hardening technique for chemically amplified positive resist, the critical dimension loss of resist pattern was prevented. 0.25 micron design rule pattern was obtained with excellent mask linearity without critical-dimension-loss. The combination techniques are achieved quarter micron design rule complex circuit pattern layouts.

Optical parameters of KrF excimer laser stepper are optimized for 0.25 µm level patterning by means of a light intensity simulation method. The light intensity simulation method is applied conventional and two modified illuminations (annular and 4-point) to improve the depth of focus (DOF) at 0.25 µm periodic lines and spaces pattern (L&S). Simulation results obtained are; (1) the DOF of conventional illumination is not sufficient even in the optimum condition (NA=0.5, σ=0.8), (2) more than 1.5 µm DOF could be achieved with an annular illumination, if present resist performance is improved slightly, and (3) wider DOF is obtained in the case of with 4-point illumination. However, the DOF is rather degraded in the specific sized (near double/triple sized) region and oblique pattern, therefore the application of this illumination is restricted into some specific mask layout pattern.

A modified illumination technique recently developed is known to improve the resolution and DOF (depth of focus) dramatically. But, it requires substantial modification in optical projection system and has some problems such as low throughput caused by low intensity and poor uniformity. And it is very difficult to adjust illumination source according to pattern changes. To solve these problems, we developed a new illumination technique, named ATOM (Advanced Tilted illumination On Mask) which applies the same concept as quadrupole illumination technique but gives many advantages over conventional techniques. This newly inserted mask gives drastic improvements in many areas such as DOF, resolution, low illumination intensity loss, and uniformity. In our experiments, we obtained best resolution of 0.28µm and 2.0µm DOF for 0.36µm feature sizes with i-line stepper, which is two times as wide as that of conventional illumination technique. We also obtained 0.22µm resolution and 2.0µm DOF for 0.28µm with 0.45NA KrF excimer laser stepper. For complex device patterns, more than 1.5 times wider DOF could be obtained compared to conventional illumination technique. From these results, we can conclude that 2nd generation of 64M DRAM with 0.3µm design rule can be printed with this technology combined with high NA (0.5) i-line steppers. With KrF excimer laser stepper, 256M DRAM can be printed with wide DOF.

A new phase shift lithography method has been developed that allows different integrated circuit features to be focused on different optical planes that conform to the wafer surface topography. In principle, each pattern in the circuit has its own unique focal plane. The direction and magnitude of each focus shift is determined by the design of the shifter patterns. This method is applicable for use with conventional opaque mask patterns and unattenuated phase shift patterns. The characteristics of this multiple-focus-plane technique have been evaluated experimentally and confirmed theoretically through mathematical modeling using TCC optical imaging theory. Experiments were conducted using i-line positive resist processes for different phase-shift patterns. This paper discusses the effects of changes in phase shift and recommends practical mask design approaches.

An electron beam cell projection system has been developed that can effectively expose the fine, demagnified resultant pattern of repeated and non-repeated patterns such as the 256 Mb DRAM on a semiconductor wafer. Particular attention was given to the beam shaping and deflecting optics, which has two stage deflectors for the cell projection beam selection as well as the beam sizing, and three stage deflectors for objective deflection. The cell mask with a rectangular aperture and multiple figure apertures is fabricated by modified Si wafer processes. A new exposure control data for the cell projection is proposed. This data is fitted for the combination of pattern data for the cell mask projection and pattern data for the variable rectangular shape beam within the divided units of the objective deflection. On this exposure system, selective exposure of the desired pattern becomes possible on the semiconductor wafer while a mounting stage of the wafer is being moved, even if the pattern exposure of the repeated and non-repeated patterns is to be carried out. The total overhead time for selecting a subset of multiple figures and a rectangular aperture of the cell mask is less than 5 seconds/wafer. The estimated throughput of this system is approximately 20 wafers/hour.

Plasma damage to gate oxide is studied using the test structures with various length antennas. It is shown that the plasma damage to gate oxide can be monitored quantitatively by measuring charge to breakdown (Q_BD). From the Q_BD measurements, it is confirmed that the degradation occurs in the duration of over-etching but not in the duration of main etching. The breakdown spots in gate oxide are detected by a photon emission method. The breakdown are caused by plasma damage at the LOCOS edge. A LOCOS structure plays an important role for the degradation by the plasma damage.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg₂SiO₄ (Forsterite) and Zn₂SiO₄ (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

Water desorption from interlayer dielectric, spin-on-glass and SiO₂ film deposited with tetraethylorthosilicate and O₃, was controlled in order to reduce MOSFET hot-carrier degradation by using plasma SiO₂ film as a water blocking layer. Two kinds of plasma SiO₂ film were used in this study: SiH₄ plasma SiO₂ film deposited with SiH₄ and N₂O, and TEOS plasma SiO₂ film deposited with TEOS and O₂. Thermal desorption spectroscopy was used to study water desorption. Reduction of water desorption was obtained using plasma SiO₂ film with water blocking ability; this reduction of water desorption resulted in suppression of the MOSFET hot-carrier degradation. The water blocking ability was obtained by low pressure deposition for SiH₄ plasma SiO₂ and low flow rate ratio of TEOS to O₂ deposition for TEOS plasma SiO₂. Water absorption studies of plasma SiO₂ film using Fourier transform infrared spectroscopy revealed that water blocking ability is associated with small amount of water absorption both in SiH₄ plasma SiO₂ film and in TEOS plasma SiO₂ film. Consequently, it is considered that the water blocking ability, as well as water absorption, of plasma SiO₂ film depends on porosity.

Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi₂ on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi₂ takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi₂ lines. The discontinuity of TiSi₂ abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi₂ by annealing at 800 for 30 seconds, while it does not occur in TiSi₂ gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.

Today, defect sources of LSI device mainly lie in the process equipments. The particles generating in these equipments are introduced onto the wafer, and form the defects resulting in functional failures of LSI device. Thus, reducing these particles is acquired for increasing production yield and higher productivity, and it is important to identify the particle source in the equipment. In this study, we discussed new two methods to identify this source in the equipment used in the production line. The important point of identifing is to estimate the particle generation with short time and high accuracy, and to minimize long time stop of the equipment requiring disassembly. First, we illustrated "particle distribution analysis method." In this method, we showed the procedure to express the particle distribution mathematically. We applied this method to our etching equipment, and could identify the particle source without stopping this etching equipment. Secondly, we illustrated the method of "in-situ particle monitoring method," and applied this method to our AP-CVD equipment. As a result, it was clear the main particle source of this equipment and the procedure for decreasing these particles. By using this method, we could estimate the particle generation at real time in process without stopping this equipment. Thus, both methods shown in this study could estimate the particle generation and identify the particle source with short time and high accuracy. Furthermore, they do not require long time stop of the process equipment and interrupting the production line. Therefore, these methods are concluded to be very useful and effective in LSI manufacturing process.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH₄OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH₄OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.

The stability conditions and stability factors of terminated active two port networks are investigated. They are expressed with the S parameters of active devices and the radii and centers of the circles defined by source and load terminations. The stability conditions are applied to specific cases. Some of the results correspond to the stability conditions expressed in Z, Y, H or G parameters and one of the other stability conditions of terminated two port network is similar to that for passive terminations which is expressed in S parameters. The various results derived in this paper are very useful for checking the stability of amplifiers, because both stability conditions and stability factors are simply calculated by using the S parameters without using the graphical method or transforming S parameters to Z, Y, H or G parameters. These stability conditions can be also used even if negative input or output resistance appears and even if the real part of source or load immittance is negative.

A modified beam propagation method based on the Galerkin's technique (FE-BPM) has been implemented and applied to the analysis of optical beam propagation in a tapered dielectric waveguide. It is based on a new calculation procedure using non-uniform sampling spacings along the transverse coordinate. Comparison with a conventional FE-BPM shows a definite improvement in saving computation time. The differences of a propagation field and a mean square power given by the proposed FE-BPM are discussed in comparison with the conventional FE-BPM.

A technique to realize a transconductance which is relatively insensitive over temperature variations is reported. Simulation results with MOS and bipolar transistors indicate substantial improvement in temperature insensitivity over a range exceeding 100 degrees Celsius. It should find useful applications in analog LSI/VLSI systems operating over a wide range of temperature.