Recent developments and case studies regarding VLSI device chip failure analysis are reviewed. The key failure analysis techniques reviewed include EMMS (emission microscopy), OBIC (optical beam induced current), LCM (liquid crystal method), EBP (electron beam probing), and FIB (focused ion beam method). Further, future possibilities in failure analysis, and some promising new tools are introduced.

Following a discussion of various testing methods used in the electron beam (EB) test system, new waveform-based and image-based approaches in the CAD-linked electron beam (EB) test system are proposed. A waveform-based automatic tracing algorithm of the transistor-level performance faults is first discussed. Then, the method to improve the efficiency of an image-based method called dynamic fault imaging (DFI) by fully utilizing the CAD data is described. Third, the VLSI development cost is analyzed by using the fault models that make possible to take into consideration the effect of new testing technologies such as EB testing and focused ion beam (FIB) microfabrication. Finally, the future prospects are discussed.

A method to improve the efficiency of dynamic fault imaging (DFI) by fully utilizing the CAD data in the CAD-linked electron beam test system is proposed. In the method, in order to shorten the long acquisition time of the stroboscopic voltage contrast images over the whole area of the chip during the entire test cycle, only the area and phase (time) required for fault tracing are selected by utilizing the CAD data. Furthermore, image processing techniques are combined with the method to improve the efficiency of the DFI. In particular, the signal averaging technique is used in order to improve the signal-to-noise ratio in the stroboscopic images where all voltage information data on the equipotential electrode recognized by the CAD layout data are averaged. This enables us to reduce the acquisition time of images. Moreover, the experimental system is set up so that the image processing can be performed in parallel with the acquisition of the stroboscopic images. The proposed method is applied to part of a 2k-transistor block of a nonpassivated CMOS LSI where a marginal fault is detected. The result shows that the method is an efficient approach to the fully automatic fault diagnosis in the CAD-linked electron beam test system. The proposed method could improve the efficiency of the conventional DFI by a factor of more than 1000.

A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.

Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.

Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.

The mechanism for data retention failure of EPROM has been investigated by the Optical Beam Induced Current(OBIC) technique. It was found that the data of failure cells were changed from '1' to '0' during read-mode by laser irradiation by OBIC. The data in good cells was not changed. This result suggests the effective barrier height between Si and SiO₂ is being lowered. In addition, the cross section technique revealed that gate electrode and gate oxide were exposed due to lack of dielectric layers. This defect seemed to be the cause of the barrier height lowering. The OBIC technique not only gives the failure location but a detailed information of the failure mechanism. We found that OBIC technique is a very powerful tool for the analysis of EPROM failure mechanisms. The usefulness of the Emission Micro Scope (EMS) technique is also discussed.

The origin of and a method of enhancing the Optical Beam Induced Resistance Change (OBIRCH) signal for defect observation in VLSI metal interconnections is discussed based on a numerical analysis of three-dimensional thermal conduction and experimental results. The numerical analysis shows that the OBIRCH signal originates from a slight increase in the resistance of the metal line caused by laser beam heating and that its effect is influenced by the temperature of the metal layer. Both simulations and experimental results suggest that cooling the sample is preferable to detect the OBIRCH signal. The decrease in the total resistance of the metal line without any change in the amount of the resistance increase under laser illumination is found to be the main cause of the OBIRCH signal enhancement under low temperature measurement.

New detection method of passivation defect was studied. The method was the Cu decoration method without bias (bias-free Cu decoration). As the result of comparison with conventional method, it was found that a bias-free Cu decoration method was effective, sensitive and simple. In this method, the difference of humidity resistance induced by poor passivation coverage could be evaluated.

A procedure for preparing a cross-sectional transmission electron microscopy (TEM) micrograph of a specific area is outlined. A specific area in a specimen has been very difficult to observe with TEM, because a particular small area cannot be preselected in the conventional specimen preparation technique using mechanical polishing, dimpling and ion milling. The technique in this paper uses a focused ion beam (FIB) to fabricate a cross-sectional specimen at a desired area. The applications of this specimen preparation technique are illustrated for investigations of particles in the process of fabricating devices and degraded aluminum/aluminum vias. The specimen preparation technique using FIB is useful for observing a specific area. This technique is also useful for shortening the time of specimen preparation and observing wide areas of LSI devices.

When intermetal oxide film which contains much water deposited on MOSFET, degradation of hot carrier characteristics is enhanced. This mechanism is considered to be as follows. During the annealing process water is desorbed from the intermetal oxide. The desorbed water reaches the MOSFET and eventually hydrogens terminate silicon dangling bonds in the gate oxide. This paper describes a new approach which uses ESR to analyze this mechanism. The ESR measurement of number of the silicon dangling bonds in undoped polysilicon lying under the intermetal oxide shows that water diffuses from intermetal oxide to MOSFET during the annealing process. The water diffusion is blocked by introduction between the polysilicon and the intermetal oxides of P-SiN layer or CVD SiO₂ damaged by implantation.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

A convenient method for determining emitter and base resistances from small signal measurements has been developed. This method is based on Neugroschel's method, but the frequency has been varied instead of varying β₀. It is demonstrated that the base resistance was successfully extracted. The extracted emitter resistance depended on the collector current because of the difference between the exact g_m value and the approximated one, I_C/V_T. It has also been shown that the proposed method is more robust than the conventional impedance-circle method even when cross-talk occurs.

This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.

Operation characteristics of tapered-waveguide traveling wave semiconductor laser amplifier (TTW-SLA) are calculated in terms of quasi adiabatic single mode propagation, signal gain and saturation output power, device efficiency(the efficiency of conversion between the electrical and amplified optical power), and amplified spontaneous emission (ASE) power, and their dependences on the shape of the taper are compared for linear, quadratic, Gaussian and exponential functions, It was found that in the allowed quasi adiabatic single mode propagation condition, linear and Gaussian TTW-SLA have higher saturation output power property, while the exponential TTW-SLA has higher device efficiency property and lower ASE noise of about 0.1 times that of a broad type TW-SLA.

An improved reflection wave method was described for measurement of complex permittivity of low-loss materials over 100MHz-1GHz range. The residual impedance Z_r and stray admittance Y_s surrounding the test sample, which terminated the transmission line, were evaluated using sapphire as a reference material. The correction by the obtained Z_r and Y_s gave accurate values of complex permittivities of alumina and mullite ceramics as 100MHz-1GHz.

We describe a geometrical optics approach for the analysis of dielectric tapered waveguides. The method is based on the ray-optical treatment for wave-normal rays defined newly to waves of light in open structures. Geometrical optics fields are represented in terms of two kinds of wave-normal rays: leaky rays and guided rays. Since the behavior of these rays is different in the two regions separated at critical incidence, the geometrical optics fields have certain classes of discontinuity in a transition region between leaky and guided regions. Guided wave solutions are given as a superposition of guided rays that zigzag along the guides, all of which are totally reflected upon the interfaces. By including some leaky rays adjacent to the guided rays, we obtain more accurate guided wave solutions. Calculated results are in excellent agreement with wave optics solutions.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.