Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis

Norio KUJI; Kazuhiro SHIRAKAWA

Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis

Norio KUJI, Kazuhiro SHIRAKAWA

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Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.4 pp.560-566

Publication Date: 1994/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Failure Analysis)

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Norio KUJI, Kazuhiro SHIRAKAWA, "Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 4, pp. 560-566, April 1994, doi: .
Abstract: Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_4_560/_p

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@ARTICLE{e77-c_4_560,
author={Norio KUJI, Kazuhiro SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis},
year={1994},
volume={E77-C},
number={4},
pages={560-566},
abstract={Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis
T2 - IEICE TRANSACTIONS on Electronics
SP - 560
EP - 566
AU - Norio KUJI
AU - Kazuhiro SHIRAKAWA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1994
AB - Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.
ER -