IEICE TRANSACTIONS on Electronics
Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
Summary :
This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.4 pp.615-623
- Publication Date
- 1994/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Kyoung-Rok CHO, Kazuma OKURA, Kunihiro ASADA, "Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 4, pp. 615-623, April 1994, doi: .
Abstract: This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_4_615/_p
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@ARTICLE{e77-c_4_615,
author={Kyoung-Rok CHO, Kazuma OKURA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)},
year={1994},
volume={E77-C},
number={4},
pages={615-623},
abstract={This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
T2 - IEICE TRANSACTIONS on Electronics
SP - 615
EP - 623
AU - Kyoung-Rok CHO
AU - Kazuma OKURA
AU - Kunihiro ASADA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1994
AB - This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.
ER -
English
