IEICE TRANSACTIONS on Electronics
Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System
Summary :
Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.4 pp.567-573
- Publication Date
- 1994/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Failure Analysis)
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Koji NAKAMAE, Ryo NAKAGAKI, Katsuyoshi MIURA, Hiromu FUJIOKA, "Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 4, pp. 567-573, April 1994, doi: .
Abstract: Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_4_567/_p
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@ARTICLE{e77-c_4_567,
author={Koji NAKAMAE, Ryo NAKAGAKI, Katsuyoshi MIURA, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System},
year={1994},
volume={E77-C},
number={4},
pages={567-573},
abstract={Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System
T2 - IEICE TRANSACTIONS on Electronics
SP - 567
EP - 573
AU - Koji NAKAMAE
AU - Ryo NAKAGAKI
AU - Katsuyoshi MIURA
AU - Hiromu FUJIOKA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1994
AB - Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.
ER -
English
