Ti Salicide Process for Subquarter-Micron CMOS Devices

Ken-ichi GOTO; Tatsuya YAMAZAKI; Yasuo NARA; Tetsu FUKANO; Toshihiro SUGII; Yoshihiro ARIMOTO; Takashi ITO

Ti Salicide Process for Subquarter-Micron CMOS Devices

Ken-ichi GOTO, Tatsuya YAMAZAKI, Yasuo NARA, Tetsu FUKANO, Toshihiro SUGII, Yoshihiro ARIMOTO, Takashi ITO

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Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi₂ on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi₂ takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi₂ lines. The discontinuity of TiSi₂ abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi₂ by annealing at 800 for 30 seconds, while it does not occur in TiSi₂ gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.3 pp.480-485

Publication Date: 1994/03/25

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Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)

Category: Process Technology

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Ken-ichi GOTO, Tatsuya YAMAZAKI, Yasuo NARA, Tetsu FUKANO, Toshihiro SUGII, Yoshihiro ARIMOTO, Takashi ITO, "Ti Salicide Process for Subquarter-Micron CMOS Devices" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 3, pp. 480-485, March 1994, doi: .
Abstract: Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi₂ on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi₂ takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi₂ lines. The discontinuity of TiSi₂ abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi₂ by annealing at 800 for 30 seconds, while it does not occur in TiSi₂ gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_3_480/_p

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@ARTICLE{e77-c_3_480,
author={Ken-ichi GOTO, Tatsuya YAMAZAKI, Yasuo NARA, Tetsu FUKANO, Toshihiro SUGII, Yoshihiro ARIMOTO, Takashi ITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ti Salicide Process for Subquarter-Micron CMOS Devices},
year={1994},
volume={E77-C},
number={3},
pages={480-485},
abstract={Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi₂ on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi₂ takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi₂ lines. The discontinuity of TiSi₂ abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi₂ by annealing at 800 for 30 seconds, while it does not occur in TiSi₂ gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Ti Salicide Process for Subquarter-Micron CMOS Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 480
EP - 485
AU - Ken-ichi GOTO
AU - Tatsuya YAMAZAKI
AU - Yasuo NARA
AU - Tetsu FUKANO
AU - Toshihiro SUGII
AU - Yoshihiro ARIMOTO
AU - Takashi ITO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1994
AB - Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi₂ on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi₂ takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi₂ lines. The discontinuity of TiSi₂ abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi₂ by annealing at 800 for 30 seconds, while it does not occur in TiSi₂ gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.
ER -