IEICE TRANSACTIONS on Electronics
New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer
Summary :
A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.5 pp.709-711
- Publication Date
- 2010/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.709
- Type of Manuscript
- LETTER
- Category
- Integrated Electronics
Authors
Keyword
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Joung-Yeal KIM, Su-Jin PARK, Yong-Ki KIM, Sang-Keun HAN, Young-Hyun JUN, Chilgee LEE, Tae Hee HAN, Bai-Sun KONG, "New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 709-711, May 2010, doi: 10.1587/transele.E93.C.709.
Abstract: A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.709/_p
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@ARTICLE{e93-c_5_709,
author={Joung-Yeal KIM, Su-Jin PARK, Yong-Ki KIM, Sang-Keun HAN, Young-Hyun JUN, Chilgee LEE, Tae Hee HAN, Bai-Sun KONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer},
year={2010},
volume={E93-C},
number={5},
pages={709-711},
abstract={A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.},
keywords={},
doi={10.1587/transele.E93.C.709},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer
T2 - IEICE TRANSACTIONS on Electronics
SP - 709
EP - 711
AU - Joung-Yeal KIM
AU - Su-Jin PARK
AU - Yong-Ki KIM
AU - Sang-Keun HAN
AU - Young-Hyun JUN
AU - Chilgee LEE
AU - Tae Hee HAN
AU - Bai-Sun KONG
PY - 2010
DO - 10.1587/transele.E93.C.709
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.
ER -
English
