We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

The composite right/left-handed (CRLH) coaxial line (CL) with wideband electromagnetic band gap (EBG) is applied to the wideband choke structure for a monocone antenna with short elements, and the resulting characteristics are considered. In the proposed antenna, impedance matching and leakage current suppression can be achieved across a wideband off. The lowest frequency (|S11| ≤ -10dB) of the proposed antenna is about the same as that of the monocone antenna on an infinite ground plane. In addition, the radiation patterns of the proposed antenna are close to the figure of eight in wideband. The proposed antenna is prototyped, and the validity of the simulation is verified through measurement.

Two kinds of composite right/left-handed coaxial lines (CRLH CLs) are designed for an antenna element. The dispersion relations of the infinite periodic CRLH CLs are designed to occur -1st resonance at around 700 MHz, respectively. The designed CRLH CLs comprise a monopole and a choke structure for antenna elements. To verify the resonant modes and frequencies, the monopole structure, the choke structure, and the antenna element which is combined the monopole and the choke structures are simulated by eigenmode analysis. The resonant frequencies correspond to the dispersion relations. The monopole and the choke structures are applied to the coaxially fed antenna. The proposed antenna matches at 710 MHz and radiates. At the resonant frequency, the total length of the proposed antenna which is the length of the monopole structure plus the choke structure is 0.12 wavelength. The characteristics of the proposed antenna has been compared with that of the conventional coaxially fed monopole antenna without the choke structure and the sleeve antenna with the quarter-wavelength choke structure. The radiation pattern of the proposed antenna is omnidirectional, the total antenna efficiency is 0.73 at resonant frequencies, and leakage current is suppressed lesser than -10 dB at resonant frequency. The propose antenna is fabricated and measured. The measured |S11| characteristics, radiation patterns, and the total antenna efficiency are in good agreement with the simulated results.

We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand both “write” and “read” stabilities, but also to achieve a low stand-by power and data holding capability in a single low power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the word-line voltages for a “read” and “write” operation, respectively. It can also adaptively lower and higher the memory cell supply voltages for the “write” and “hold” operations, and “read” operation, respectively. This paper focuses on the “hold” characteristics and the standby power dissipations (PST) of the developed SRAM. The average PST of the developed SRAM is only 0.984µW, namely, 9.57% of that (10.28µW) of the conventional SRAM at a supply voltage (VDD) of 1.0V. The data hold margin of the developed SRAM is 0.1839V and that of the conventional SRAM is 0.343V at the supply voltage of 1.0V. An area overhead of the SVL circuit is only 1.383% of the conventional SRAM.

As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.

We propose a novel IDDQ outlier screening flow through a two-phase approach: a clustering-based filtering and an estimation-based current-threshold determination. In the proposed flow, a clustering technique first filters out chips that have high IDDQ current. Then, in the current-threshold determination phase, device-parameters of the unfiltered chips are estimated based on measured IDDQ currents through Bayesian inference. The estimated device-parameters will further be used to determine a statistical leakage current distribution for each test pattern and to calculate a and suitable current-threshold. Numerical experiments using a virtual wafer show that our proposed technique is 14 times more accurate than the neighbor nearest residual (NNR) method and can achieve 80% of the test escape in the case of small leakage faults whose ratios of leakage fault sizes to the nominal IDDQ current are above 40%.

With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.

We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

In this letter, a novel body bias selection scheme for minimizing the leakage of MOS transistors is presented. The proposed scheme directly monitors leakages at present and adjacent body bias voltages, and dynamically updates the voltage at which the leakage is minimized regardless of process and temperature variations. Comparison results in a 46 nm CMOS technology indicated that the proposed scheme achieved leakage reductions of up to 68% as compared to conventional body biasing schemes.

Ba0.5Sr0.5Ta2O6 (BSTA) thin film was successfully fabricated on a Pt/SiO2/TiO2/Si substrate using the Sol-Gel method. Fundamental electrical properties of the BSTA thin film were investigated using metal-insulator-metal (MIM) structure. No diffusion of ions, from the thin film or the substrate, is observed because of the using of MIM structure. The Root Mean Square roughness of 1.04 nm shows that thin film grew well on the substrate. The BSTA thin film shows a much higher dielectric constant of about 130 than conventional gate insulators and high-k materials that are currently used in Thin Film Transistors. Low leakage current density of about 10-8 A/cm2 was obtained at an applied electric field of 500 kV/cm. Schottky emission is the dominant conduction mechanism at applied electric fields lower than 500 kV/cm and Fowler-Nordheim tunneling is the dominant conduction mechanism at higher applied electric fields. The Schottky barrier height between the Pt electrode and the Ba0.5Sr0.5Ta2O6 thin film was estimated to be 0.75 eV.

This paper presents the new switching converter model used for analyzing the generation mechanism of ringing ground leakage (GL) current, generated during the transient, at switch on/off of any switching converter. By applying the Norton model, the proposed new model of switching converter can be formulated. The ringing GL current is evaluated at the switching on/off of the unbalanced (half-bridge converter) and the balanced converter (full-bridge converter) for bidirectional D.C. motor drive used as an example. It is concluded that the measured and simulated results of the generated GL current agree well with the numerical analysis results, analyzed by the proposed new model of switching converter, in terms of the minimum or maximum peak currents and the ringing frequency.

A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.

Leakage current for MOSFET in off-state is one of the serious problems in charge-based analog circuits under low power supply. To suppress the leakage current, a method that a slight voltage is applied to source to accomplish reverse bias between source and bulk is proposed. The proposed bias condition, also other bias conditions, is analyzed by injection carrier density in p-n junction and surface carrier concentration in MOS diode in four-terminal MOSFET. Leakage current is modeled by combining the characteristics of p-n junction with MOS diode in MOSFET. The characteristics of MOSFET fabricated with a standard 0.18 µm n-well CMOS technology are measured to investigate the basic principle. Measured leakage current fits to the theoretical leakage current exactly. The proposed slight bias to source terminal in MOSFET is proved most efficient to reduce the leakage current. Based on the proposed source bias condition, MOSFET switches with low leakage current under a single power supply are proposed.

To reduce the gate leakage current of AlGaN/GaN HEMTs, we selected ITO/Ni/Au for Schottky electrodes and Schottky characteristics were compared with those of Ni/Au electrodes. ITO/Ni/Au and Ni/Au electrodes were deposited by vacuum evaporation and annealed at 350 in nitrogen atmosphere. From the I-V evaluation results of ITO/Ni/Au electrodes, forward and reverse leakage currents were reduced. Schottky characteristics of ITO/Ni/Au electrodes were also improved compared to these of Ni/Au electrodes. In addition, substantial decrease of leakage currents was confirmed after the annealing of HEMTs with ITO/Ni/Au electrodes. This may be explained that ITO/AlGaN interface state became lower by the annealing. By the temperature dependence of I-V curves, clear dependence was confirmed for the gates with ITO/Ni/Au electrodes. On the other hand, small dependence was observed for those with Ni/Au electrodes. From these results, tunnel leakage currents were dominant for the gates with Ni/Au electrode. Thermal emission current was dominant for the gates with ITO/Ni/Au electrode. The larger temperature dependence was caused that ITO/AlGaN interface states were smaller than those for Ni/Au electrode. It was suggested that suppressed AlGaN Schottky barrier thinning was caused by the surface defect donors, then tunneling leakage currents were decreased. We evaluated HEMT characteristics with ITO/Ni/Au electrode and Ni/Au electrode. Id max and Gm max were similar characteristics, but Vth with ITO/Ni/Au electrode was shifted +0.4 V than that with Ni/Au electrode due to the higher Schottky barrier. It was confirmed to have a good pinch-off currents and low gate leakage currents by ITO/Ni/Au electrodes.

PIN diodes for digital X-ray detection as a single photon counting sensor were fabricated on a floating-zone (FZ) n-type (111), high resistivity (5-10 kΩcm) silicon substrates (500 µm thickness). Its electrical properties such as the leakage current and the breakdown voltage were characterized. The size of pixels was 100 µm100 µm. The p+ guard-ring was formed around the active area to reduce the leakage current. After the p+ active area and guard-ring were fabricated by the ion-implantation, the extrinsic-gettering on the wafer backside was performed to reduce the leakage current by n+ ion-implantation. PECVD oxide was deposited as an IMD layer on front side and then, metal lines were formed on both sides of wafers. The leakage current of detectors was significantly reduced with a guard-ring when compared with that without a guard ring. The leakage current showed the strong dependency on the gap distance between the active area and the guard ring. It was possible to achieve the leakage current lower than 0.2 nA/cm2.

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for 40% or more of the total energy consumed in these systems. Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Consequently, a Temperature-Aware Configurable Cache (TACC) is an effective way to save energy in finer technologies when the embedded system is used in different temperatures. Our results show that using a TACC, up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner-case temperature (100). Furthermore, the TACC also enhances the performance by up to 28% for the instruction cache and up to 17% for the data cache.