IEICE TRANSACTIONS on Fundamentals
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC
Summary :
As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1442-1454
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1442
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Gong CHEN
Design Algorithm Laboratory, Inc.
Yu ZHANG
University of Kitakyushu
Qing DONG
University of Kitakyushu
Ming-Yu LI
University of Kitakyushu
Shigetoshi NAKATAKE
University of Kitakyushu
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Gong CHEN, Yu ZHANG, Qing DONG, Ming-Yu LI, Shigetoshi NAKATAKE, "Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1442-1454, July 2015, doi: 10.1587/transfun.E98.A.1442.
Abstract: As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1442/_p
Copy
@ARTICLE{e98-a_7_1442,
author={Gong CHEN, Yu ZHANG, Qing DONG, Ming-Yu LI, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC},
year={2015},
volume={E98-A},
number={7},
pages={1442-1454},
abstract={As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.},
keywords={},
doi={10.1587/transfun.E98.A.1442},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1442
EP - 1454
AU - Gong CHEN
AU - Yu ZHANG
AU - Qing DONG
AU - Ming-Yu LI
AU - Shigetoshi NAKATAKE
PY - 2015
DO - 10.1587/transfun.E98.A.1442
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.
ER -
English
