We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.
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Michihiro SHINTANI, Takashi SATO, "Device-Parameter Estimation through IDDQ Signatures" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 2, pp. 303-313, February 2013, doi: 10.1587/transinf.E96.D.303.
Abstract: We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.303/_p
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@ARTICLE{e96-d_2_303,
author={Michihiro SHINTANI, Takashi SATO, },
journal={IEICE TRANSACTIONS on Information},
title={Device-Parameter Estimation through IDDQ Signatures},
year={2013},
volume={E96-D},
number={2},
pages={303-313},
abstract={We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.},
keywords={},
doi={10.1587/transinf.E96.D.303},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - Device-Parameter Estimation through IDDQ Signatures
T2 - IEICE TRANSACTIONS on Information
SP - 303
EP - 313
AU - Michihiro SHINTANI
AU - Takashi SATO
PY - 2013
DO - 10.1587/transinf.E96.D.303
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2013
AB - We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.
ER -