We have developed a low bit-rate video coding using a video digital signal processor (DSP) called VDSP1χ, which performs real-time encoding and decoding for discrete cosine transform-(DCT-) based algorithms, such as ITU-T H. 261, H. 263 and wavelet-based subband encoding algorithms. This LSI features a processing unit which implements wavelet filters at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. This system is capable of processing quarter common intermediate format (QCIF)(176144 pixels) size pictures at a rate greater than 15 frames/s.

A low power MPEG-4 video codec LSI with the capability for core profile decoding is presented. A 16-b DSP with a vector pipeline architecture and a 32-b arithmetic unit, eight dedicated hardware engines to accelerate MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing, 20-Mb embedded DRAM, and three peripheral blocks are integrated together on a single chip. MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing are realized with a hybrid architecture consisting of a programmable DSP and dedicated hardware engines at low operating frequency. In order to reduce the power consumption, clock gating technique is fully adopted in each hardware block and embedded DRAM is employed. The chip is implemented using 0.18-µm quad-metal CMOS technology, and its die area is 8.8 mm 8.6 mm. The power consumption is 90 mW at a SP@L1 codec and 110 mW at a CP@L1 decoding.