1-4hit |
Ramesh K. POKHAREL Kenta UCHIDA Abhishek TOMAR Haruichi KANAYA Keiji YOSHIDA
A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 µm CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 µm CMOS technology, and tested. The measured phase noise of DCO was -118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.
Ramesh K. POKHAREL Shashank LINGALA Awinash ANAND Prapto NUGROHO Abhishek TOMAR Haruichi KANAYA Keiji YOSHIDA
This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.
Ramesh K. POKHAREL Prapto NUGROHO Awinash ANAND Abhishek TOMAR Haruichi KANAYA Keiji YOSHIDA
High phase noise is a common problem in ring oscillators. Continuous conduction of the transistor in an analog tuning method degrades the phase noise of ring oscillators. In this paper, a digital control tuning which completely switches the transistors on and off, and a 1/f noise reduction technique are employed to reduce the phase noise. A 14-bit control signal is employed to obtain a small frequency step and a wide tuning range. Furthermore, multiphase ring oscillator with a sub-feedback loop topology is used to obtain a stable quadrature outputs with even number of stages and to increase the output frequency. The measured DCO has a frequency tuning range from 554 MHz to 2.405 GHz. The power dissipation is 112 mW from 1.8 V power supply. The phase noise at 4 MHz offset and 2.4 GHz center frequency is -134.82 dBc/Hz. The FoM is -169.9 dBc/Hz which is a 6.3 dB improvement over the previous oscillator design.
Abhishek TOMAR Shashank LINGALA Ramesh K. POKHAREL Haruichi KANAYA Keiji YOSHIDA
An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.