IEICE TRANSACTIONS on Electronics
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays
Summary :
CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.10 pp.1540-1543
- Publication Date
- 2010/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.1540
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
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Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH, "Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 10, pp. 1540-1543, October 2010, doi: 10.1587/transele.E93.C.1540.
Abstract: CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1540/_p
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@ARTICLE{e93-c_10_1540,
author={Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays},
year={2010},
volume={E93-C},
number={10},
pages={1540-1543},
abstract={CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.},
keywords={},
doi={10.1587/transele.E93.C.1540},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays
T2 - IEICE TRANSACTIONS on Electronics
SP - 1540
EP - 1543
AU - Jinn-Shyan WANG
AU - Yu-Juey CHANG
AU - Chingwei YEH
PY - 2010
DO - 10.1587/transele.E93.C.1540
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2010
AB - CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.
ER -
English
