Recent embedded systems require both traditional machinery control and information processing, such as network and GUI handling. A dual-OS platform consolidates a real-time OS (RTOS) and general-purpose OS (GPOS) to realize efficient software development on one physical processor. Although the dual-OS platform attracts increasing attention, it often suffers from energy inefficiency in the GPOS for guaranteeing real-time responses of the RTOS. This paper proposes an energy minimization method called DVFS virtualization, which allows running multiple DVFS policies dedicated to the RTOS and GPOS, respectively. The experimental evaluation using a commercial microcontroller showed that the proposed hardware could change the supply voltage within 500 ns and reduce the energy consumption of typical applications by 60 % in the best case compared to conventional dual-OS platforms. Furthermore, evaluation using a commercial microprocessor achieved a 15 % energy reduction of practical open-source software at best.

Adaptive voltage scaling is a promising approach to overcome manufacturing variability, dynamic environmental fluctuation, and aging. This paper focuses on error prediction based adaptive voltage scaling (EP-AVS) and proposes a mean time to failure (MTTF) aware design methodology for EP-AVS circuits. Main contributions of this work include (1) optimization of both voltage-scaled circuit and voltage control logic, and (2) quantitative evaluation of power saving for practically long MTTF. Experimental results show that the proposed EP-AVS design methodology achieves 38.0% power saving while satisfying given target MTTF.

For battery based real-time embedded systems, high performance to meet their real-time constraints and energy efficiency to extend battery life are both essential. Real-Time Dynamic Voltage Scaling (RT-DVS) has been a key technique to satisfy both requirements. This paper presents EccEDF (Enhanced ccEDF), an efficient algorithm based on ccEDF. ccEDF is one of the most simple but efficient RT-DVS algorithms. Its simple structure enables it to be easily and intuitively coupled with a real-time operating system without incurring any significant cost. ccEDF, however, overlooks an important factor in calculating the available slacks for reducing the operating frequency. It calculates the saved utilization simply by dividing the slack by the period without considering the time needed to run the task. If the elapsed time is considered, the maximum utilization saved by the slack on completion of the task can be found. The proposed EccEDF can precisely calculate the maximum unused utilization with consideration of the elapsed time while keeping the structural simplicity of ccEDF. Further, we analytically establish the feasibility of EccEDF using the fluid scheduling model. Our simulation results show that the proposed algorithm outperforms ccEDF in all simulations. A simulation shows that EccEDF consumes 27% less energy than ccEDF.

This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

The past decade has seen a surge of research activities in the fields of mobile computing and wireless communication. In particular, recent technological advances have made portable devices, such as PDA, laptops, and wireless modems to be very compact and affordable. To effectively operate portable devices, energy efficiency and Quality of Service (QoS) provisioning are two primary concerns. Dynamic Voltage Scaling (DVS) is a common method for energy conservation for portable devices. However, due to the amount of data that needs to be dynamically handled in varying time periods, it is difficult to apply conventional DVS techniques to QoS sensitive multimedia applications. In this paper, a new adaptive DVS algorithm is proposed for QoS assurance and energy efficiency. Based on the repeated learning model, the proposed algorithm dynamically schedules multimedia service requests to strike the appropriate performance balance between contradictory requirements. Experimental results clearly indicate the performance of the proposed algorithm over that of existing schemes.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.

The principles for good design of battery-aware voltage scheduling algorithms for both aperiodic and periodic task sets on dynamic voltage scaling (DVS) systems are presented. The proposed algorithms are based on greedy heuristics suggested by several battery characteristics and Lagrange multipliers. To construct the proposed algorithms, we use the battery characteristics in the early stage of scheduling more properly. As a consequence, the proposed algorithms show superior results on synthetic examples of periodic and aperiodic tasks from the task sets which are excerpted from the comparative work, on uni- and multi-processor platforms, respectively. In particular, for some large task sets, the proposed algorithms enable previously unschedulable task sets due to battery exhaustion to be schedulable.

We propose a dynamic voltage scaling algorithm to exploit the temporal locality called TLDVS (Temporal Locality DVS) that can achieve significant energy savings while simultaneously preserving timeliness guarantees made by real-time scheduling. Traditionally hard real-time scheduling algorithms assume that the actual computation requirement of tasks would be varied continuously from time to time, but most real-time tasks have a limited number of operational modes changing with temporal locality. Such temporal locality can be exploited for energy savings by scaling down the operating frequency and the supply voltage accordingly. The proposed algorithm does not assume task periodicity, and requires only previous execution time among a priori information on the task set to schedule. Simulation results show that TLDVS achieves up to 25% energy savings compared with OLDVS, and up to 42% over the non-DVS scheduling.

Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

In real-time embedded systems, there is requirement for adapting both energy consumption and Quality of Services (QoS) of tasks according to their importance. This paper proposes an adaptive power-aware resource allocation method to resolve a trade-off between the energy consumption and QoS levels according to their importance with guaranteeing fairness. The proposed resource allocator consists of two components: the total resource optimizer to search for the optimal total resource and QoS-fairness-based allocator to allocate resource to tasks guaranteeing the fairness. These components adaptively achieve the optimal resource allocation formulated by a nonlinear optimization problem with the time complexity O(n) for the number of tasks n even if tasks' characteristics cannot be identified precisely. The simulation result shows that the rapidness of the convergence of the resource allocation to the optimal one is suitable for real-time systems with large number of tasks.

This paper describes novel CMOS level-conversion flip-flops for use in low-power SoCs with clustered voltage scaling. These flip-flops feed outputs directly into the front stage to support self-resetting and conditional operations. They thus have simple structures to avoid clock level shifting and redundant transitions, leading to substantial improvements in terms of power and area. The comparison results indicate that the proposed level-conversion flip-flops achieve power and area savings up to 50% and 31%, respectively, with no speed degradation as compared to conventional level-conversion flip-flops.

A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when VDDL/VDDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.

Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.