In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

This paper presents a novel low-energy memory design technique based on variable analysis for on-chip data memory (RAM) in application-specific systems, which called VAbM technique. It targets the exploitation of both data locality and effective data width of variables to reduce energy consumed by data transfer and storage. Variables with higher access frequency and smaller effective data width are assigned into a smaller low-energy memory with fewer bit lines and word lines, placed closer the processor. Under constraints of the number of memory banks, VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple banks, which have different size with different number of word lines and different number of bit lines tailored to each application requirements. Experimental results with several real embedded applications demonstrate significant energy reduction up to 64.8% over monolithic memory, and 27.7% compared to memory designed by memory banking technique.

In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

A multi-application smart card system consists of an issuer, service vendors and cardholders, where cardholders are recipients of smart cards (from the issuer) to be used in connection with applications offered by service vendors. Authentic post-issuance program modification is necessary for a multi-application smart card system because applications in the system are realized after the issuance of a smart card. In this paper, we propose a system where only authentic modification is possible. In the proposed system, the smart card issuer stores a unique long bitstring called PID in a smart card. The smart card is then given to the cardholder. A unique substring of the PID (subPID) is shared between the cardholder and a corresponding service vendor. Another subPID is shared between the issuer and the cardholder. During program modification, a protocol using the subPIDs, a one-way hash function and a pseudorandom number generator function verifies the identity of the parties and the authenticity of the program.

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Behavioral extraction from circuit description is a useful technique for logic design verification. We have proposed a technique of extraction from combinational circuits and developed a prototype system. To use this system practically, it is necessary to deal with sequential circuits. In this paper, we will present a new technique to extract behavioral descriptions from synchronous sequential circuits which include some flip-flops. Flip-flops are classified to two types. The one is a part of control registers. The other is a part of data registers. Behavior of the circuit with control registers is described by the state transition. Behavior of the circuit with data registers is described by the movement of data among registers. There are many circuits, as micro processors, which realize a function after some times of state transitions occurred. In such circuits, it is more important to abstract the function than to extract each state transition. We have progressed our system to extract such behaviors.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

A new applicative design language is proposed for developing generators of data-path modules from hardware algorithms. The language includes a set of primitives that represent placement operations, parameterized cells, routing patterns and a set of transformation rules specifying modifications of the module topology without changing its functionality. Using the language, a hardware algorithm designer can easily define both the topological and geometrical specifications of module generation directly at the functional level without engaged in the layout details. A sketch of the language and an example of module design with the language is presented.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i) BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii) External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii) The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.