The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.

This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

Industrial applications such as automotive ones require a cheap communication mechanism to send out communication messages from node to node by their deadline time. This paper presents a design paradigm in which we optimize both assignment of a network node to a bus and slot multiplexing of a FlexRay network system under hard real-time constraints so that we can minimize the cost of wire harness for the FlexRay network system. We present a cost minimization problem as a non-linear model. We developed a network synthesis tool which was based on simulated annealing. Our experimental results show that our design paradigm achieved a 50.0% less cost than a previously proposed approach for a virtual cost model.

Character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask manufacture because it can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we first present a projection mask set development methodology for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and VSB lithographies. Next, we present an INLP (integer nonlinear programming) model as well as an ILP (integer linear programming) model for optimizing a CP mask set of an MCC projection system so that projection time is reduced. The experimental results show that our optimization has achieved 33.4% less projection time in the best case than a naive CP mask development approach. The experimental results indicate that our CP mask set optimization method has virtually increased cell pattern objects on CP masks and has decreased VSB projection so that it has achieved higher projection throughput than just parallelizing two column-cells with conventional CP masks.

Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic continuous signature monitoring (DCSM) technique for high reliable computer systems. The DCSM technique dynamically generates reference signatures as well as runtime ones during executing a program. The DCSM technique stores the generated signatures in a signature table, which is a small storage circuit in a microprocessor, unlike the conventional static continuous signature monitoring techniques and contributes to saving program or data memory space that stores the signatures. Our experiments showed that our DCSM technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to soft errors, has not been taken into account in the conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor as a vulnerability measure for computer systems so that we evaluate task-wise reliability over various processor structures. Next we build a mixed integer linear programming (MILP) model for minimizing the chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i) BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii) External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii) The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper discusses reliability inherent in heterogeneous multiprocessors and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints.

This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error model identifies which part of memory modules are utilized temporally and spatially and which single event upsets (SEUs) are critical to the program execution of the computer system at the cycle accurate instruction set simulation (ISS) level. The soft-error model is capable of estimating reliability of a computer system that has several memory hierarchies with it and finding which memory module is vulnerable in the computer system. Reliability estimation helps system designers apply reliable design techniques to vulnerable part of their design. The experimental results have shown that the usage of the soft-error model achieved more accurate reliability estimation than conventional approaches. The experimental results demonstrate that reliability of computer systems depends on not only soft error rates (SERs) of memories but also the behavior of software running in computer systems.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

We propose a character size optimization technique to reduce the number of EB shots of multi-column-cell (MCC) lithographic systems in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for ICs. Experimental results show that the character size optimization achieved 70.6% less EB shots in the best case with an available electron beam (EB) size. Our technique also achieved 40.6% less EB shots in the best case than a conventional character sizing technique.

We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.