IEICE TRANSACTIONS on Fundamentals
Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Summary :
We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2632-2638
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- IP Protection
Authors
Keyword
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Vikram IYENGAR, Hiroshi DATE, Makoto SUGIHARA, Krishnendu CHAKRABARTY, "Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2632-2638, November 2001, doi: .
Abstract: We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2632/_p
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@ARTICLE{e84-a_11_2632,
author={Vikram IYENGAR, Hiroshi DATE, Makoto SUGIHARA, Krishnendu CHAKRABARTY, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores},
year={2001},
volume={E84-A},
number={11},
pages={2632-2638},
abstract={We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2632
EP - 2638
AU - Vikram IYENGAR
AU - Hiroshi DATE
AU - Makoto SUGIHARA
AU - Krishnendu CHAKRABARTY
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
ER -
English
