IEICE TRANSACTIONS on Fundamentals
Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Summary :
In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.12 pp.2621-2629
- Publication Date
- 1998/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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- Compiler
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Hiroyuki TOMIYAMA, Tohru ISHIHARA, Akihiko INOUE, Hiroto YASUURA, "Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2621-2629, December 1998, doi: .
Abstract: In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2621/_p
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@ARTICLE{e81-a_12_2621,
author={Hiroyuki TOMIYAMA, Tohru ISHIHARA, Akihiko INOUE, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches},
year={1998},
volume={E81-A},
number={12},
pages={2621-2629},
abstract={In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2621
EP - 2629
AU - Hiroyuki TOMIYAMA
AU - Tohru ISHIHARA
AU - Akihiko INOUE
AU - Hiroto YASUURA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
ER -
English
