IEICE TRANSACTIONS on Fundamentals
Module Selection Using Manufacturing Information
Summary :
Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.12 pp.2576-2584
- Publication Date
- 1998/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-level Synthesis
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Keyword
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Hiroyuki TOMIYAMA, Hiroto YASUURA, "Module Selection Using Manufacturing Information" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2576-2584, December 1998, doi: .
Abstract: Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2576/_p
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@ARTICLE{e81-a_12_2576,
author={Hiroyuki TOMIYAMA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Module Selection Using Manufacturing Information},
year={1998},
volume={E81-A},
number={12},
pages={2576-2584},
abstract={Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Module Selection Using Manufacturing Information
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2576
EP - 2584
AU - Hiroyuki TOMIYAMA
AU - Hiroto YASUURA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
ER -
English
