Design of High-Performance CMOS Level Converters Considering PVT Variations
Summary :
CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.5 pp.913-916
- Publication Date
- 2011/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.913
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH, "Design of High-Performance CMOS Level Converters Considering PVT Variations" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 5, pp. 913-916, May 2011, doi: 10.1587/transele.E94.C.913.
Abstract: CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.913/_p
Copy
@ARTICLE{e94-c_5_913,
author={Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of High-Performance CMOS Level Converters Considering PVT Variations},
year={2011},
volume={E94-C},
number={5},
pages={913-916},
abstract={CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.},
keywords={},
doi={10.1587/transele.E94.C.913},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - Design of High-Performance CMOS Level Converters Considering PVT Variations
T2 - IEICE TRANSACTIONS on Electronics
SP - 913
EP - 916
AU - Jinn-Shyan WANG
AU - Yu-Juey CHANG
AU - Chingwei YEH
PY - 2011
DO - 10.1587/transele.E94.C.913
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2011
AB - CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.
ER -
English
