CMOS Level Converter with Balanced Rise and Fall Delays
Summary :
A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.1 pp.192-195
- Publication Date
- 2007/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.1.192
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Min-su KIM, Young-Hyun JUN, Sung-Bae PARK, Bai-Sun KONG, "CMOS Level Converter with Balanced Rise and Fall Delays" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 1, pp. 192-195, January 2007, doi: 10.1093/ietele/e90-c.1.192.
Abstract: A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.1.192/_p
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@ARTICLE{e90-c_1_192,
author={Min-su KIM, Young-Hyun JUN, Sung-Bae PARK, Bai-Sun KONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Level Converter with Balanced Rise and Fall Delays},
year={2007},
volume={E90-C},
number={1},
pages={192-195},
abstract={A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.},
keywords={},
doi={10.1093/ietele/e90-c.1.192},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - CMOS Level Converter with Balanced Rise and Fall Delays
T2 - IEICE TRANSACTIONS on Electronics
SP - 192
EP - 195
AU - Min-su KIM
AU - Young-Hyun JUN
AU - Sung-Bae PARK
AU - Bai-Sun KONG
PY - 2007
DO - 10.1093/ietele/e90-c.1.192
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2007
AB - A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.
ER -
English
