Bitcoin is one of popular cryptocurrencies widely used over the world, and its blockchain technology has attracted considerable attention. In Bitcoin system, it has been reported that transactions are prioritized according to transaction fees, and that transactions with high priorities are likely to be confirmed faster than those with low priorities. In this paper, we consider performance modeling of Bitcoin-blockchain system in order to characterize the transaction-confirmation time. We first introduce the Bitcoin system, focusing on proof-of-work, the consensus mechanism of Bitcoin blockchain. Then, we show some queueing models and its analytical results, discussing the implications and insights obtained from the queueing models.

In maritime networks, the communication links are characterized as high dynamics due to ship mobility and fluctuation of the sea surface. The performance of traditional transmission protocols is poor in maritime networks. Thus, some researchers have considered using Delay Tolerant Network (DTN) to improve the performance of data transmission in maritime environment. Most existing work on maritime DTNs uses simulation to evaluate the transmission performance in maritime DTNs. In this paper, we develop a theoretical model to analyze the performance of data transmission in maritime DTNs. We first construct a model to describe the ship encounter probability. Then, we use this model to analyze the data delivery ratio from ships in the seaway to the base station (BS) on the coast. Based on the data of tracing the ships navigating in a realistic seaway, we develop a simulator and validate the theoretical models. In addition, by comparing the performance of DTN transmission protocol and traditional end-to-end transmission protocol, we confirm that DTN protocol can effectively improve the performance of data transmission in maritime networks.

Online resource management of a software system can take advantage of a performance model to predict the effect of proposed changes. However, the prediction accuracy may degrade if the performance model does not adapt to the changes in the system. This work considers the problem of using Kalman filters to track changes in both performance model parameters and system behavior. We propose a method based on the multiple-model Kalman filter. The method runs a set of Kalman filters, each of which models different system behavior, and adaptively fuses the output of those filters for overall estimates. We conducted case studies to demonstrate how to use the method to track changes in various system behaviors: performance modeling, process modeling, and measurement noise. The experiments show that the method can detect changes in system behavior promptly and significantly improve the tracking and prediction accuracy over the single-model Kalman filter. The influence of model design parameters and mode-model mismatch is evaluated. The results support the usefulness of the multiple-model Kalman filter for tracking performance model parameters in systems with time-varying behavior.

The interference rejection combining (IRC) receiver, which can suppress inter-cell interference, is effective in improving the cell-edge user throughput. The IRC receiver is typically based on the minimum mean square error (MMSE) criteria, and requires a covariance matrix including the interference signals, in addition to a channel matrix from the serving cell. Therefore, in order to clarify the gain from the IRC receiver, the actual estimation error of these matrices should be taken into account. In a system performance evaluation, the link performance modeling of the IRC receiver, i.e., the output signal-to-interference-plus-noise power ratio (SINR) after IRC reception including the estimation errors, is very important in evaluating the actual performance of the IRC receiver in system level simulations. This is because these errors affect the suppression of the interference signals for the IRC receiver. Therefore, this paper investigates and proposes IRC receiver modeling schemes for the covariance matrix and channel estimation errors. As the modeling scheme for the covariance matrix, we propose a scheme that averages the conventional approximation using the complex Wishart distribution in the frequency domain to address issues that arise in a frequency selective fading channel. Furthermore, we propose a modeling scheme for the channel estimation error according to the ideal channel response of all cells and a channel estimation filter to address channel fading fluctuations. The results of simulations assuming the LTE/LTE-Advanced downlink with two transmitter and receiver antenna branches show that the proposed modeling scheme for the covariance matrix estimation error accurately approximates the performance of a realistic IRC receiver, which estimates the covariance matrix and channel matrix of the serving cell based on the demodulation reference signal (DM-RS), even in a frequency selective fading channel. The results also show that the proposed modeling scheme for the channel estimation error is a robust scheme in terms of the r.m.s. delay spread of a channel model compared to the scheme using the mean square error (MSE) statistic of the estimated channel coefficients based on a channel estimation filter.

This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

Given the availability of high-speed Ethernet and HW based protocol offload, clustered systems using a commodity network fabric (e.g., TCP/IP over Ethernet) are expected to become more attractive for a range of e-business and data center applications. In this paper, we describe a comprehensive simulation to study the performance of clustered database systems using such a fabric. The simulation model currently supports both TCP and SCTP as the transport protocol and models an Oracle 9i like clustered DBMS running a TPC-C like workload. The model can be used to study a wide variety of issues regarding the performance of clustered DBMS systems including the impact of enhancements to network layers (transport, IP, MAC), QoS mechanisms or latency improvements, and cluster-wide power control issues.

It has been a very important issue to evaluate the performance of transmission control protocol (TCP), and the importance is still growing up because TCP will be deployed more widely in future wireless as well as wireline networks. It is also the reason why there have been a lot of efforts to analyze TCP performance more accurately. Most of these works are focusing on overall TCP end-to-end throughput that is defined as the number of bytes transmitted for a given time period. Even though each TCP's fast recovery strategy should be considered in computation of the exact time period, it has not been considered sufficiently in the existing models. That is, for more detailed performance analysis of a TCP implementation, the fast recovery latency during which lost packets are retransmitted should be considered with its relevant strategy. In this paper, we extend the existing models in order to capture TCP's loss recovery behaviors in detail. On the basis of the model, the loss recovery latency of three TCP implementations can be derived with considering the number of retransmitted packets. In particular, the proposed model differentiates the loss recovery performance of TCP using selective acknowledgement (SACK) option from TCP NewReno. We also verify that the proposed model reflects the precise latency of each TCP's loss recovery by simulations.

A method for fast but yet accurate performance evaluation of processor architecture is mostly desirable in modern processors design. This paper proposes one such method which can measure cycle counts and power consumption of pipelined processors. The method first develops a trace-driven performance simulation model and then employs simulation reuse in simulation of the model. The trace-driven performance modeling is for accuracy in which performance simulation uses the same execution traces as constructed in simulation for functional verification. Fast performance simulation can be achieved in a way that performance for each instruction in the traces is evaluated without evaluation of the instruction itself. Simulation reuse supports simulation speedup by elimination of an evaluation at the current state, which is identical to that at a previous state. The reuse approach is based on the property that application programs, especially multimedia applications, have many iterative loops in general. A performance simulator for pipeline architecture based on the proposed method has been developed through which greater speedup has been made compared with other approaches in performance evaluation.

We investigate a state dependent multicast routing scheme, called Least Load Multicast Routing (LLMR), for single rate loss networks. The algorithm is based on Least Load Routing (LLR) concept and the approach is to select the least loaded links for establishing connections. An analytical model for LLMR is developed. The accuracy of the analytical model is compared with the simulation results and is found to be very good. We also develop a simplified analytical model for fully symmetrical networks, which is also verified by comparing with simulation results.

In Optimistic Two-Phase Locking (O2PL), when a transaction requests a commit, the transaction can not be committed until all requested locks are obtained. By this reason, O2PL leads to unnecessary waits and operations even though it adopts an optimistic approach. This paper suggests an efficient optimistic cache consistency protocol that provides serializability of committed transactions. Our cache consistency scheme, called PCP (Preemptive Cache Protocol), decides whether to commit or abort without waiting when transactions request commits. In PCP, some transactions that read stale data items can not be aborted, because it adopts a re-ordering scheme to enhance the performance. In addition, for re-ordering, PCP stores only one version of each data item. This paper presents a simulation-based analysis on the performance of PCP with other protocols such as O2PL, Optimistic Concurrency Control and Caching Two-Phase Locking. The simulation experiments show that PCP performs as well as or better than other schemes with low overhead.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.