Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051

Je-Hoon LEE; YoungHwan KIM; Kyoung-Rok CHO

Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051

Je-Hoon LEE, YoungHwan KIM, Kyoung-Rok CHO

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In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.527-534

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Je-Hoon LEE, YoungHwan KIM, Kyoung-Rok CHO, "Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 527-534, April 2004, doi: .
Abstract: In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_527/_p

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@ARTICLE{e87-c_4_527,
author={Je-Hoon LEE, YoungHwan KIM, Kyoung-Rok CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051},
year={2004},
volume={E87-C},
number={4},
pages={527-534},
abstract={In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051
T2 - IEICE TRANSACTIONS on Electronics
SP - 527
EP - 534
AU - Je-Hoon LEE
AU - YoungHwan KIM
AU - Kyoung-Rok CHO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.
ER -