This study proposes a new asynchronous Multi-Rate Multiple-Access Differential Chaos Shift Keying (MRMA-DCSK) scheme, ensuring significant data rates for all users. This scheme assigns a unique chaos sequence with a different length to each user. During the first data transmission period, each user transmits the chaos sequence as the reference signal, followed by multiple data bits by sharing the same reference signal in subsequent periods. The proposed scheme affects the bit-error-rate (BER) performance with the number of users, data rate related parameters (L), and length of chaos signals. The simulation results are verified by the derived analysis and show that the proposed scheme achieves higher data rates (from 1/2 to L/L+1) than a conventional scheme while enhancing bit-error-rate (BER) performance.

This paper introduces a deep reinforcement learning approach to solve the virtual network function scheduling problem in dynamic scenarios. We formulate an integer linear programming model for the problem in static scenarios. In dynamic scenarios, we define the state, action, and reward to form the learning approach. The learning agents are applied with the asynchronous advantage actor-critic algorithm. We assign a master agent and several worker agents to each network function virtualization node in the problem. The worker agents work in parallel to help the master agent make decision. We compare the introduced approach with existing approaches by applying them in simulated environments. The existing approaches include three greedy approaches, a simulated annealing approach, and an integer linear programming approach. The numerical results show that the introduced deep reinforcement learning approach improves the performance by 6-27% in our examined cases.

Non-orthogonal multiple access (NOMA) allows several users to multiplex in the power-domain to improve spectral efficiency. To further improve its performance, it is desirable to reduce inter-user interference (IUI). In this paper, we propose a downlink asynchronous NOMA (ANOMA) scheme applicable to frequency-selective channels. The proposed scheme introduces an intentional symbol offset between the multiplexed signals to reduce IUI, and it employs cyclic-prefixed single-carrier transmission with frequency-domain equalization (FDE) to reduce inter-symbol interference. We show that the mean square error for the FDE of the proposed ANOMA scheme is smaller than that of a conventional NOMA scheme. Simulation results show that the proposed ANOMA with appropriate power allocation achieves a better sum rate compared to the conventional NOMA.

This paper proposes a novel interference cancellation technique that prevents radio receivers from degrading due to periodic interference signals caused by electromagnetic waves emitted from high power circuits. The proposed technique cancels periodic interference signals in the frequency domain, even if the periodic interference signals drift in the time domain. We propose a drift estimation based on a super resolution technique such as ESPRIT. Moreover, we propose a sequential drift estimation to enhance the drift estimation performance. The proposed technique employs a linear filter based on the minimum mean square error criterion with assistance of the estimated drifts for the interference cancellation. The performance of the proposed technique is confirmed by computer simulation. The proposed technique achieves a gain of more than 40dB at the higher frequency part in the band. The proposed canceler achieves such superior performance, if the parameter sets are carefully selected. The proposed sequential drift estimation relaxes the parameter constraints, and enables the proposed cancellation to achieve the performance upper bound.

In this paper, we propose four optimization methods during the Register Transfer Level (RTL) conversion from synchronous RTL models into asynchronous RTL models. The modularization of data-path resources and the use of appropriate D flip-flops reduce the circuit area. Fixing the control signal of the multiplexers and inserting latches for the data-path resources reduce the dynamic power consumption. In the experiment, we evaluated the effect of the proposed optimization methods. The combination of all optimization methods could reduce the energy consumption by 21.9% on average compared to the ones without the proposed optimization methods.

In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.

Boolean networks (BNs) are considered as popular formal models for the dynamics of gene regulatory networks. There are many different types of BNs, depending on their updating scheme (synchronous, asynchronous, deterministic, or non-deterministic), such as Classical Random Boolean Networks (CRBNs), Asynchronous Random Boolean Networks (ARBNs), Generalized Asynchronous Random Boolean Networks (GARBNs), Deterministic Asynchronous Random Boolean Networks (DARBNs), and Deterministic Generalized Asynchronous Random Boolean Networks (DGARBNs). An important long-term behavior of BNs, so-called attractor, can provide valuable insights into systems biology (e.g., the origins of cancer). In the previous paper [1], we have studied properties of attractors of GARBNs, their relations with attractors of CRBNs, also proposed different algorithms for attractor detection. In this paper, we propose a new algorithm based on SAT-based bounded model checking to overcome inherent problems in these algorithms. Experimental results prove the effectiveness of the new algorithm. We also show that studying attractors of GARBNs can pave potential ways to study attractors of ARBNs.

In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.

The methods proposed in this paper enable resynchronization when a synchronization deviation occurs in a sensor node without a beacon or an ack in a wireless sensor network under ultra-limited but stable resources such as the energy generated from tiny solar cell batteries. The method for a single-hop network is straightforward; when a receiver does not receive data, it is simply placed in recovery mode, in which the receiver sets its cycle length TB to (b±γ)T, where b is non-negative integer, 0 < γ < 1, and T is its cycle length in normal mode, and in which the receiver sets its active interval WB to a value that satisfies WB ≥ W + γT, where W is its active interval in normal mode. In contrast, a sender stays in normal mode. Resynchronization methods for linear multi-hop and tree-based multi-hop sensor networks are constructed using the method for a single-hop network. All the methods proposed here are complete because they are always able to resynchronize networks. The results of simulations based on the resynchronization methods are given and those of an experiment using actual sensor nodes with wireless modules are also presented, which show that the methods are feasible.

This paper shows an optimal spreading sequence in the Weyl sequence class, which is similar to the set of the Oppermann sequences for asynchronous CDMA systems. Sequences in Weyl sequence class have the desired property that the order of cross-correlation is low. Therefore, sequences in the Weyl sequence class are expected to minimize the inter-symbol interference. We evaluate the upper bound of cross-correlation and odd cross-correlation of spreading sequences in the Weyl sequence class and construct the optimization problem: minimize the upper bound of the absolute values of cross-correlation and odd cross-correlation. Since our optimization problem is convex, we can derive the optimal spreading sequences as the global solution of the problem. We show their signal to interference plus noise ratio (SINR) in a special case. From this result, we propose how the initial elements are assigned, that is, how spreading sequences are assigned to each users. In an asynchronous CDMA system, we also numerically compare our spreading sequences with other ones, the Gold codes, the Oppermann sequences, the optimal Chebyshev spreading sequences and the SP sequences in Bit Error Rate. Our spreading sequence, which yields the global solution, has the highest performance among the other spreading sequences tested.

Code division multiple access (CDMA) based on direct sequence (DS) spread spectrum modulation using spreading codes is one of standard technologies for multiple access communications. In asynchronous DS/CDMA communications, spreading codes with appropriate negative auto-correlation can reduce bit error rate (BER) compared with uncorrelated sequences. In this letter, we design new binary functions for generating chaotic binary sequences with negative auto-correlation using Bernoulli chaotic map. Such binary functions can be applied to the generation of spreading codes with negative auto-correlation based on existing spreading codes (e.g., shift register sequences).

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

Multiple-way (N-way) asynchronous arbitration is an important issue in asynchronous system design. In this paper, novel implementation methods of N-way asynchronous arbiters are presented. We first present N-way rectangle mesh arbiters using 2-way mutual exclusion elements. Then, N-way token-ring arbiters based on the non-return-to-zero signaling is also presented. The former can issue grant signals with the same percentage for all the arriving request signals while the latency is proportional to the number of inputs. The latter can achieve low latency and low energy arbitration for a heavy workload environment and a large number of inputs. In this paper, we compare their performances using the 28nm FD-SOI process technologies qualitatively and quantitatively.

In recent 3GPP (3rd Generation Partnership Project) standardization meetings, D2D (Device-to-Device) discovery has been a major issue to support commercial/social services and public safety in disaster environment, and TDM (Time Division Multiplexing) based discovery channel structure is mainly considered to prevent mutual interference between D2D and cellular traffic. In this structure, D2D discovery among the same cell UEs (User Equipment) has no problem because they have the same timing source. However, LTE (Long Term Evolution) assumes an asynchronous network where two adjacent eNBs (evolved Node B) have a symbol-level timing offset. For that reason, asynchronous interference among discovery signals can appear in inter-cell D2D discovery. Therefore, channel re-use scheduling was studied previously in which neighboring cells do not use the same portion of the extended discovery channel and other non-neighboring cells re-use it. However, it still shows interference problems in small cell networks which cause substantial cellular traffic loss. Therefore, in this paper, we propose a novel discovery channel scheduling in which eNBs time-align their discovery channels from each other by sample-level. In the proposed scheme, serving eNB requests cell edge UEs to estimate NTD (Network Time Difference) between serving eNB and neighboring eNB. Then, considering multiple NTDs, eNB adjusts the sample position of its discovery channel based on a novel decision rule. We verify that the proposed scheme can match the discovery performance of a synchronous network with less cellular uplink loss.

The mammalian cochlear consists of highly nonlinear components: lymph (viscous fluid), a basilar membrane (vibrating membrane in the viscous fluid), outer hair cells (active dumpers for the basilar membrane), inner hair cells (neural transducers), and spiral ganglion cells (parallel spikes density modulators). In this paper, a novel spiral ganglion cell model, the dynamics of which is described by an asynchronous cellular automaton, is presented. It is shown that the model can reproduce typical nonlinear responses of the spiral ganglion cell in the mammalian cochlea, e.g., spontaneous spiking, parallel spike density modulation, and adaptation. Also, FPGA experiments validate reproductions of these nonlinear responses.

In this paper, we propose a new design technique called extit{asynchronous multi-frequency clocking} for suppressing EMI at a chip design level by combining two independent EMI-suppressing approaches: extit{multi-frequency clocking} and extit{asynchronous circuit design} techniques. To show the effectiveness of our approach, a five-stage pipelined asynchronous MIPS with multi-frequency clocking has been implemented on a commercial Xilinx FPGA device. Our approach shows 11.05 dB and 5.88 dB reductions of peak EM radiation in the prototyped implementation when compared to conventional synchronous and bundled-data asynchronous circuit counterparts, respectively.

Stochastic decoding provides ultra-low-complexity hardware for high-throughput parallel low-density parity-check (LDPC) decoders. Asynchronous stochastic decoding was proposed to demonstrate the possibility of low power dissipation and high throughput in stochastic decoders, but decoding might stop before convergence due to “lock-up”, causing error floors that also occur in synchronous stochastic decoding. In this paper, we introduce a wire-delay dependent (WDD) scheduling algorithm for asynchronous stochastic decoding in order to reduce the error floors. Instead of assigning the same delay to all computation nodes in the previous work, different computation delay is assigned to each computation node depending on its wire length. The variation of update timing increases switching activities to decrease the possibility of the “lock-up”, lowering the error floors. In addition, the WDD scheduling algorithm is simplified for the hardware implementation in order to eliminate time-averaging and multiplication functions used in the original WDD scheduling algorithm. BER performance using a regular (1024, 512) (3,6) LDPC code is simulated based on our timing model that has computation and wire delay estimated under ASPLA 90nm CMOS technology. It is demonstrated that the proposed asynchronous decoder achieves a 6.4-9.8× smaller latency than that of the synchronous decoder with a 0.25-0.3 dB coding gain.

An energy-efficient intra-chip communication link circuit with ternary current signaling is proposed for an asynchronous Network-on-Chip. The data signal encoded by an asynchronous three-state protocol is represented by a small-voltage-swing three-level intermediate signal, which results in the reduction of transition delay and achieving energy-efficient data transfer. The three-level voltage is generated by using a combination of dynamically controlled current sources with feedback loop mechanism. Moreover, the proposed circuit contains a power-saving scheme where the dynamically controlled transistors also are utilized. By cutting off the current paths when the data transfer on the communication link is inactive, the power dissipation can be greatly reduced. It is demonstrated that the average data-transfer speed is about 1.5 times faster than that of a binary CMOS implementation using a 130nm CMOS technology at the supply voltage of 1.2V.

This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).

A modern system-on-chip (SoC) includes many heterogeneous IP components. Generally, a few embedded processors are integrated into SoCs. An asynchronous circuit design technique is employed to achieve low power/energy consumption. In this paper, we design an asynchronous embedded processor on FPGAs and analyze its possible benefits on commercial FPGAs. We use commercially available 65nm high-performance Virtex-5 and 45nm low-power Spartan-6 Xilinx FPGAs to show the impact on power consumption for the two different extreme cases. For the high performance Virtex-5, our asynchronous processor shows 36.8% lower power consumption when compared with its synchronous counterpart. On the other hand, the asynchronous processor consumes 25.6% more power in a low power Spartan-6 FPGA. However, through simple analysis and power simulation, we show that the event-driven nature of asynchronous circuits can further save power/energy even in the Spartan-6 FPGA.