In this paper, we consider conventional signaling link fault tolerance and error correction mechanisms to provide reliable services of mobile multimedia telecommunication network based on ATM (Asynchronous Transfer Mode) technology. Also, we propose an efficient signaling protocol interworking architecture and a reliable distributed interworking network architecture between SS7 based FPLMTS and ATM networks. Besides, we evaluate the performance of proposed method through computer simulation. According to the results, proposed signaling architecture shows efficient and fast fault restoration characteristics than conventional MTP-3/3b based network. Functional signaling protocol stack and network architecture of proposed fast rerouting mechanism provide reliable and efficient restoration performance in view of interworking between SS7 based FPLMTS and ATM networks.

In this paper, we propose a quasi-optimum multiuser detector using co-channel interference cancellation technique in an asynchronous code-division multiple-access communication system, and evaluate its performance by computer simulations. In the proposed detector, maximum likelihood sequence estimation is performed to compare the original received signal with replicas of the signal which are produced from the demodulation data bit sequence of a co-channel interference canceller. In several conditions, the proposed detector is compared with the co-channel interference canceller, and it is shown that the average bit error rate characteristics of the propose detector are improved considerably.

This paper discribes a shared medium access control protocol for residential home and small business customer ATM network application with distributed high-speed multimedia services. This protocol offers global fairness for the whole network with a CG (Centralized Grant) signal and, at the same time, offers local fairness between nodes with DG (Distributed Grant) signals. The DG signal is only meaningful to the next neighboring node. The local fairness is kept between two nodes in distributed way, but this distributed local fairness helps to keep the global fairness. Because the DG signal is related to the passed DG signal from the neighbor node. This protocol is rather simple but shows high performance than the already announced protocols.

In this paper, we analyze the individual sojourn delay experienced by cells from each virtual channel (VC) passing through an ATM switch port. Traffic from each VC is described by a four-parameter Markov-Modulated Bernoulli process (MMBP). A switch port is assumed to receive traffic from a group of heterogeneous MMBPs and the queueing behavior is modelled by a H-MMBPs/D/1/ queue. Two service disciplines are considered: FIFO and priority. Closed-form formulas of overall as well as individual sojourn delays for both service disciplines are obtained. Although approximation is inevitable in our analysis, the accuracy is good when compare with computer simulations. As a result we provide an efficient tool to estimate cell delay for each individual VC before it is established. Our result can be applied to network resource decision or control problems such as call admission control and routing.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

We apply a novel methodology, based on statecharts, to the design of large scale asynchronous systems. The design is specified at multiple levels, simulated, animated, and compiled into synthesizable VHDL code by using the ExpressV-HDL CAD tool. We add a validation sub-system to chech correct operation. ExpressV-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependence on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronous circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.

Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self-timed design technique, based on the Muller model, improves performance by eliminating the global clock. In order to prevent hazard, a self-timed system should satisfy certain assumptions and timing constraints, therefore special cells are required. The novel Self-timed Cell Library is designed for 1.2µm CMOS technology which contains Muller C-elements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provides a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog simulator; (3) It is flexible since it is compatible with an existing Standard Cell Library. In this paper, the library is described. Moreover, the simulated and measured cell characteristics are compared. Using the library, two [18] [81] matrix multipliers employing (1) DCVSL technique, and (2) micropipeline technique have been implemented as design examples and the results are compared. In addition, this paper also demonstrates the benefits of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also proposed.

An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.

In this paper, a new two-level flow control scheme using VP credit-based control and stop-and-go rate control for Asynchronous Transfer Mode (ATM) networks is presented. Since the proposed scheme does not require any information on traffic characteristics, we propose to apply such a flow control scheme to the best effort traffic that requires no band-width guarantee from the network. The proposed flow control scheme can efficiently use the leftover bandwidth after the guaranteed traffic has been satisfied. Therefore, high bandwidth utilization can be achieved. Furthermore, cell loss can completely be avoided by the lower-level credit-flow control done on a per VP basis. On top of this, a higher-level Explicit Congestion Notification (ECN) rate control is employed to avoid any performance degradation. Simulations have been performed to verify the effectiveness of the proposed scheme. It is found that the average end-to-end delay of our proposed scheme is better than that of the original VCFC scheme [1]. In addition, there is also a tremendous saving in the memory required when compared with the VCFC scheme.

Intricate Speech Communication Mode (I-SC Mode) is observed in verbal interaction during ISDN-TV conferencing. It is characterized by conflicts and multiple interactions of speech. I-SC Mode might cause mental stress to participants and be obstacles for smooth communication. However, the reasons of I-SC Mode on the environment of information transmission are hitherto unknown. Furthermore, analyses on the talks inside a conference site (LT: local talk or a talk inside a local site) and between remote sites (MT: media talk or a talk between remote sites) are originally conceived on assumed differences in cognitive distance and media intimacy. This study deals with communication effects/barriers and cognitive distance/intimacy of media correlated with audio-video transmission signals and speech modes or talk types and response delay in human speech interactions by using an innovated conference model (decision-making transaction model: DT-Model) in synchronous ISDN-TV conference systems (SYN) and asynchronous ones (ASYN). The effects of intricate communication can be predicted to a certain extent and in some ways. In I-SC Mode, because a timely answer can not be received from recipients (or partner), response time delay and response rate are analyzed. These factors are thus analyzed with an innovated dynamic model, where the recognizable acceptance of delay is evaluated. The nonlinear model shows that the larger the response time delay, the lower the response rate becomes. Comparing the response rate between SYN and ASYN, the latter is notably lower than the former. This indicates that the communication efficiency is lower in ASYN. An I-SC Mode is the main mode that occurs during ASYN conferences, and this in turn causes psychological stress. Statistics show the prevalence of a high incidence of complicated plural talks and a low response rate exists as the main factors preventing smooth human-to-human communication. Furthermore, comparing the response delays in face-to-face LT (Tf) and machine-mediated MT (Tm), human communication delay is significantly extended by the effects of initial mechanical delays. Therefore, cognitive intimacy of media is clearly affected by the existence of physical distance.

Signal Transition Graphs (STG'S) [1] are Petrinets [2], which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfollding, has been proposed [3], [4]. OCN's can represent both causality and concurrency between two nodes by net stryctyre. In this paper, we propose an efficient algorithm to derive a logic function by generating sub-state space of a given STG using the structural properties of OCN. The proposed algorithm can be seem as a parallel algorithm for deriving a logic function.

This paper shows that a network supplying variable bit rate services can be prevented from becoming congested if each terminal limits the capacity of its connection in terms of its rate of increase. Variable bit rate sources are adequately assessed with two new concepts: the bit rate increase per unit time (acceleration-rate=αbit/sec2) or the bit rate increase ratio (acceleration-ratio=exp (β) ). The dimension of the acceleration-ratio coefficient βis seconds-1. The upper limits α and β are regulated to guarantee the network's QoS. The proposed concepts allow the network state to be accurately estimated and avoid congestion. The proposed method can be applied to ATM networks, Frame Relay networks, Fast Reservation Protocol systems and so on.

This paper concerns multiple-valued logical function realized by asynchronous circuit that may have feed-back loops and its completeness problems. The first aim is to give mathematical definition of an asynchronous circuit over multiple-valued logical functions and of the realization of multiple-valued logical function by means of an asynchronous circuit. For asynchronous element, the definition of circuit construction and initialization are very sensitive. A slight modification may have a considerable influence on the completeness. We consider three types of completeness (LF-, GS-, NS-completeness) for a set of multiple-valued logical functions. The LF-completeness means completeness of logical functions realized loop-free cirucit. The GS-completeness means completeness under general initialization assumption. The NS-completeness measn completeness under initialization by input assumption. The second aim is to give a completeness criterion for each type of completeness. This aim is realized for LF-completeness in general case and GS-completeness in ternary case. A completeness criteria for GS-completeness and NS-completeness are given under strong conditions.

This letter proposes a new shaping algorithm (CRSA: CDV Reduction Shaping Algorithm) that can freely reduce the maximum CDV value of a cell stream to any predetermined value. There is a trade off between shaping delay and the maximum CDV value reduction achieved when using CRSA. The shaper using CRSA (CR-shaper) output satisfies the Peak Cell Rate Reference Algorithm set with the CR-shaper parameters.

Air interfaces of the future mobile communication are widely spreading, because of the multimedia service demands, technology trends and radio propagation conditions. Radio-Highway Networks are expected to realize the universal, seamless and multi-air-interface capability for mobile access networks, and play an important role in the future multimedia radio communications. For the radio-highway networks, this paper newly proposes natural bandpass sampling - asynchronous time division multiple access (NBS-ATDMA) method, where radio signals are natural bandpass sampled at the radio base station and are asynchronously multiplexed on the optic fiber bus link and intelligently transmitted to its desired radio control station. We theoretically analyze the loss probability of the radio signal due to collision in the network and the carrier-to-noise power ratio of received radio signals at the radio control station. Moreover, in order to reduce the loss probability, two access control methods, carrier sense and pulse width control, are proposed, and it is clarified that these improve the number of base station connected to radio highway networks.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

A new high-performance fault-tolerant ATM switching network is proposed. This network contains the baseline network and has many redundant switching elements to enhance the fault tolerance and throughput of the conventional multistage interconnection networks. The presented routing algorithm is very simple and can support a very huge number of paths between each input-output pair. The paths can be used to route cells when internal cell contentions occur in switching elements. The redundant switching elements at the last stage offer two access points to the output ports to resolve the output conflict. Performance analysis and simulation results show that this network has better maximum throughput even for faulty conditions. Among various networks, it has the largest number of redundant paths, and the greatest unit node contribution and unit edge contribution.