Completion-Detection Techniques for Asynchronous Circuits
Summary :
An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.3 pp.344-350
- Publication Date
- 1997/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
- Category
- Completion-Detection & Checking
Authors
Keyword
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Eckhard GRASS, Viv BARTLETT, Izzet KALE, "Completion-Detection Techniques for Asynchronous Circuits" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 3, pp. 344-350, March 1997, doi: .
Abstract: An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_3_344/_p
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@ARTICLE{e80-d_3_344,
author={Eckhard GRASS, Viv BARTLETT, Izzet KALE, },
journal={IEICE TRANSACTIONS on Information},
title={Completion-Detection Techniques for Asynchronous Circuits},
year={1997},
volume={E80-D},
number={3},
pages={344-350},
abstract={An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Completion-Detection Techniques for Asynchronous Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 344
EP - 350
AU - Eckhard GRASS
AU - Viv BARTLETT
AU - Izzet KALE
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 1997
AB - An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.
ER -
English
