An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.