IEICE TRANSACTIONS on Fundamentals
A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints
Summary :
In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E103-A No.12 pp.1427-1436
- Publication Date
- 2020/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2020VLP0006
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Tatsuki OTAKE
the University of Aizu
Hiroshi SAITO
the University of Aizu
Keyword
Latest Issue
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Tatsuki OTAKE, Hiroshi SAITO, "A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 12, pp. 1427-1436, December 2020, doi: 10.1587/transfun.2020VLP0006.
Abstract: In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020VLP0006/_p
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@ARTICLE{e103-a_12_1427,
author={Tatsuki OTAKE, Hiroshi SAITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints},
year={2020},
volume={E103-A},
number={12},
pages={1427-1436},
abstract={In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.},
keywords={},
doi={10.1587/transfun.2020VLP0006},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1427
EP - 1436
AU - Tatsuki OTAKE
AU - Hiroshi SAITO
PY - 2020
DO - 10.1587/transfun.2020VLP0006
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2020
AB - In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.
ER -
English
