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A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints

Tatsuki OTAKE, Hiroshi SAITO

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Summary :

In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E103-A No.12 pp.1427-1436
Publication Date
2020/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.2020VLP0006
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Tatsuki OTAKE
  the University of Aizu
Hiroshi SAITO
  the University of Aizu

Keyword