Design of q-Parallel LFSR-Based Syndrome Generator
Summary :
This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E98-C No.7 pp.594-596
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E98.C.594
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Seung-Youl KIM
Chungbuk National University
Kyoung-Rok CHO
Chungbuk National University
Je-Hoon LEE
Kangwon National University
Keyword
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Seung-Youl KIM, Kyoung-Rok CHO, Je-Hoon LEE, "Design of q-Parallel LFSR-Based Syndrome Generator" in IEICE TRANSACTIONS on Electronics,
vol. E98-C, no. 7, pp. 594-596, July 2015, doi: 10.1587/transele.E98.C.594.
Abstract: This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.594/_p
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@ARTICLE{e98-c_7_594,
author={Seung-Youl KIM, Kyoung-Rok CHO, Je-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of q-Parallel LFSR-Based Syndrome Generator},
year={2015},
volume={E98-C},
number={7},
pages={594-596},
abstract={This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.},
keywords={},
doi={10.1587/transele.E98.C.594},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Design of q-Parallel LFSR-Based Syndrome Generator
T2 - IEICE TRANSACTIONS on Electronics
SP - 594
EP - 596
AU - Seung-Youl KIM
AU - Kyoung-Rok CHO
AU - Je-Hoon LEE
PY - 2015
DO - 10.1587/transele.E98.C.594
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2015
AB - This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.
ER -
English
