This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.

Error control codes have extensively been applied to semiconductor memories using high density RAM chips with wide I/O data, e.g., with 8-bit or 16-bit I/O data. Recently, spotty byte errors called s-spotty byte errors are newly defined as t or fewer bits errors in a byte having length b bits, where 1 ≤ t ≤ b. This paper proposes another type of spotty byte errors, i.e., m-spotty byte errors, where more than t bits errors in a byte may occur due to hit by high energetic particles. For these errors, this paper presents generalized m-spotty byte error control codes with minimum m-spotty distance d.

Spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems using recent high-density RAM chips with wide I/O data, e.g., 8, 16, or 32 bits. A spotty byte error is defined as t-bit errors within a byte of length b-bit, where 1 ≤ t ≤ b, and denoted as t/b-error. This paper proposes a new error model of two spotty byte errors occurring simultaneously, i.e., t/b-error and t′/b-error, where t t′, called complex spotty byte errors. This paper presents two complex m-spotty byte error control codes, i.e., St/bEC-(St/b+St′/b)ED codes which correct all single t/b-errors and detect both t/b-errors and t′/b-errors simultaneously, and (St/b+St′/b)EC codes which correct both single t/b-errors and single t′/b-errors simultaneously. This paper also presents practical examples of the codes with parameter t′=1, that is, St/bEC-(St/b+S)ED codes and (St/b+S) EC codes which require smaller check-bit length than the existing Single t/b-error Correcting and Double t/b-error Detecting (St/bEC-Dt/bED) codes and the Double t/b-error Correcting (Dt/bEC) codes, respectively.

This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

This paper presents an adaptive rate error control scheme for digital communication over time-varying channels. The cyclic code with majority-logic decoding is used in a cascaded way as an inner code to create a simple and powerful hybrid-ARQ error control scheme. Inner code is used only for error correction and the outer code is used for both error correction and error detection. When an error is detected, retransmission is required. The unsuccessful packets are not discarded as with conventional schemes, but are combined with their retransmitted copies. Approximations for the throughput efficiency and the undetectable error probability are given. A high reliability coupled with a simple high-speed implementation makes it suitable for high data rate error control over both stationary and nonstationary channels. Adaptive error control scheme becomes the best solution for time-varying channels when the optimum code is selected according to the actual channel conditions to enhance the system performance. The main feature of this system is that the basic structure of the encoder and decoder need not be modified while the error-correction capability of the code increases. Results of a comparative analysis show that the proposed scheme outperforms other similar ARQ protocols.

The paper considers the design of two families of binary block codes developed for controlling large numbers of errors which may occur in LSI, optical disks and other devices. The semidistance codes are capable of assuring a required signal-to-noise ratio in information retrieval; the t-symmetric error correcting/all unidirectional error detecting" (t-SyEC/AUED) codes are capable of correcting t or fewer symmetric errors and also detecting any number of unidirectional errors caused by the asymmetric nature of transmission or storage madia. The paper establishes an equivalence between these families of codes, and proposes improved methods for constructing, for any values of t, a class of nonsystematic constant weight codes as well as a class of systematic codes. The constructed codes of both classes are shown to be optimal when t is O, and of asymptotically optimal order" in general cases. The number of redundant bits of the obtained nonsystematic code is of the order of (t+1/2)log2 K bits, where K is the amount of information encoded. The obtained systematic codes have redundancy of the order of (t+1)log2 K bits.

This letter considers a subclass of t-symmetric error correcting/all unidirectional error detecting (t-SyEC/AUED) codes in which the information is represented in an m-out-of-k coded form, which thus can be regarded as virtually systematic for practical purposes. For t3, previous researchers proposed methods for constructing codes of this subclass which are either optimal or of asymptotically optimal order. This letter proposes a new method for constructing, for any values of t, m and k, codes that are either optimal or of asymptotically optimal order. The redundancy of the obtained code is of the order tlog2k bits when mt.