IEICE TRANSACTIONS on Fundamentals
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies
Summary :
With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.5 pp.1059-1074
- Publication Date
- 2014/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.1059
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Li DING
Waseda University
Zhangcai HUANG
Waseda University
Atsushi KUROKAWA
Waseda University
Jing WANG
Waseda University
Yasuaki INOUE
Waseda University
Keyword
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Li DING, Zhangcai HUANG, Atsushi KUROKAWA, Jing WANG, Yasuaki INOUE, "An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 5, pp. 1059-1074, May 2014, doi: 10.1587/transfun.E97.A.1059.
Abstract: With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.1059/_p
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@ARTICLE{e97-a_5_1059,
author={Li DING, Zhangcai HUANG, Atsushi KUROKAWA, Jing WANG, Yasuaki INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies},
year={2014},
volume={E97-A},
number={5},
pages={1059-1074},
abstract={With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.},
keywords={},
doi={10.1587/transfun.E97.A.1059},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1059
EP - 1074
AU - Li DING
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Jing WANG
AU - Yasuaki INOUE
PY - 2014
DO - 10.1587/transfun.E97.A.1059
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2014
AB - With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.
ER -
English
