IEICE TRANSACTIONS on Fundamentals
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
Summary :
In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.847-855
- Publication Date
- 2006/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.4.847
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Keyword
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Atsushi KUROKAWA, Akira KASEBE, Toshiki KANAMOTO, Yun YANG, Zhangcai HUANG, Yasuaki INOUE, Hiroo MASUDA, "Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 4, pp. 847-855, April 2006, doi: 10.1093/ietfec/e89-a.4.847.
Abstract: In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.847/_p
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@ARTICLE{e89-a_4_847,
author={Atsushi KUROKAWA, Akira KASEBE, Toshiki KANAMOTO, Yun YANG, Zhangcai HUANG, Yasuaki INOUE, Hiroo MASUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills},
year={2006},
volume={E89-A},
number={4},
pages={847-855},
abstract={In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.},
keywords={},
doi={10.1093/ietfec/e89-a.4.847},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 847
EP - 855
AU - Atsushi KUROKAWA
AU - Akira KASEBE
AU - Toshiki KANAMOTO
AU - Yun YANG
AU - Zhangcai HUANG
AU - Yasuaki INOUE
AU - Hiroo MASUDA
PY - 2006
DO - 10.1093/ietfec/e89-a.4.847
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.
ER -
English
