IEICE TRANSACTIONS on Fundamentals
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Summary :
In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3367-3374
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3367
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Prediction and Analysis
Authors
Keyword
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Zhangcai HUANG, Atsushi KUROKAWA, Jun PAN, Yasuaki INOUE, "Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3367-3374, December 2005, doi: 10.1093/ietfec/e88-a.12.3367.
Abstract: In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3367/_p
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@ARTICLE{e88-a_12_3367,
author={Zhangcai HUANG, Atsushi KUROKAWA, Jun PAN, Yasuaki INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew},
year={2005},
volume={E88-A},
number={12},
pages={3367-3374},
abstract={In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3367},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3367
EP - 3374
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Jun PAN
AU - Yasuaki INOUE
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3367
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.
ER -
English
