IEICE TRANSACTIONS on Fundamentals
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
Summary :
Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.5 pp.1201-1209
- Publication Date
- 2011/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.1201
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Qiang LI, Bin LIN, Yasuaki INOUE, "A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 5, pp. 1201-1209, May 2011, doi: 10.1587/transfun.E94.A.1201.
Abstract: Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1201/_p
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@ARTICLE{e94-a_5_1201,
author={Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Qiang LI, Bin LIN, Yasuaki INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect},
year={2011},
volume={E94-A},
number={5},
pages={1201-1209},
abstract={Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.},
keywords={},
doi={10.1587/transfun.E94.A.1201},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1201
EP - 1209
AU - Minglu JIANG
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Qiang LI
AU - Bin LIN
AU - Yasuaki INOUE
PY - 2011
DO - 10.1587/transfun.E94.A.1201
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2011
AB - Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.
ER -
English
