IEICE TRANSACTIONS on Fundamentals
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
Summary :
In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.10 pp.2562-2569
- Publication Date
- 2005/10/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.10.2562
- Type of Manuscript
- Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Zhangcai HUANG, Atsushi KUROKAWA, Yasuaki INOUE, Junfa MAO, "A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 10, pp. 2562-2569, October 2005, doi: 10.1093/ietfec/e88-a.10.2562.
Abstract: In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.10.2562/_p
Copy
@ARTICLE{e88-a_10_2562,
author={Zhangcai HUANG, Atsushi KUROKAWA, Yasuaki INOUE, Junfa MAO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads},
year={2005},
volume={E88-A},
number={10},
pages={2562-2569},
abstract={In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.},
keywords={},
doi={10.1093/ietfec/e88-a.10.2562},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2562
EP - 2569
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Yasuaki INOUE
AU - Junfa MAO
PY - 2005
DO - 10.1093/ietfec/e88-a.10.2562
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2005
AB - In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
ER -
English
