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In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance *C _{eff}* concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.10 pp.2531-2539

- Publication Date
- 2009/10/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E92.A.2531

- Type of Manuscript
- Special Section PAPER (Special Section on Nonlinear Theory and its Applications)

- Category
- Nonlinear Problems

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Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Shuai FANG, Yasuaki INOUE, "Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 10, pp. 2531-2539, October 2009, doi: 10.1587/transfun.E92.A.2531.

Abstract: In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance *C _{eff}* concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2531/_p

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@ARTICLE{e92-a_10_2531,

author={Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Shuai FANG, Yasuaki INOUE, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model},

year={2009},

volume={E92-A},

number={10},

pages={2531-2539},

abstract={In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance *C _{eff}* concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and

keywords={},

doi={10.1587/transfun.E92.A.2531},

ISSN={1745-1337},

month={October},}

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TY - JOUR

TI - Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2531

EP - 2539

AU - Minglu JIANG

AU - Zhangcai HUANG

AU - Atsushi KUROKAWA

AU - Shuai FANG

AU - Yasuaki INOUE

PY - 2009

DO - 10.1587/transfun.E92.A.2531

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E92-A

IS - 10

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - October 2009

AB - In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance *C _{eff}* concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and

ER -